AVS 45th International Symposium
    Manufacturing Science and Technology Group Tuesday Sessions
       Session MS-TuA

Paper MS-TuA3
Dual Damascene : Etching Process Characterisation of "Self Aligned" and "Counter Bore" Architectures

Tuesday, November 3, 1998, 2:40 pm, Room 317

Session: Process, Integration, and Modeling
Presenter: P. Berruyer, LETI-GRESSI, France
Authors: P. Berruyer, LETI-GRESSI, France
F. Vinet, LETI-GRESSI, France
H. Feldis, SGS-Thomson, France
E. Tabouret, LETI-GRESSI, France
Y. Trouillet, LETI-GRESSI, France
Y. Morand, SGS-Thomson, France
Correspondent: Click to Email
One of the main challenges of the next few years is the improvement of interconnect performances, namely integration density and dynamic performances. This can not be done without combining improvement in both design and technology. In term of technology, different ways are explored : introduction of low k dielectric and low resistivity metal. Concerning low resistivity metal, copper seems to be the best candidate to replace AlCu. But the main disadvantage of this material is its high resistance to plasma etching. Taking into account that copper is highly resistant to plasma etching, that Chemical Mechanical Polishing processes are available and that dual damascene architecture can significantly increase interconnect density, copper is usually introduced in a damascene architecture. Among the different ways of achieving dual damascene structures, two of them, called " self aligned " and " counter bore " have to be taken into account. In this paper we will first describe the process steps of these two architectures. We will point out that both architectures require the development of a specific high aspect ratio dielectric etching process with high selectivity to nitride. A medium density reactor (TEL Unity DRM) will be used for the experiments. Different process conditions will be applied to dual damascene structures for a morphological characterisation. Major attention will be paid on selectivity to nitride, microloading, etch stop and CD control. Etch rate and selectivity to photoresist will also be studied. The architectures and the etching processes will be compared on an electrical lot with copper metallisation. Contact resistance and yield on 10 million contact chains will be measured. The advantage and drawbacks of each architecture will be discussed with regard to etching processes. An optimised dual damascene process will be proposed.