AVS 45th International Symposium
    Manufacturing Science and Technology Group Tuesday Sessions
       Session MS-TuA

Invited Paper MS-TuA1
Pattern/Etch/Clean Process Interactions for 0.18um CMOS Gate Formation

Tuesday, November 3, 1998, 2:00 pm, Room 317

Session: Process, Integration, and Modeling
Presenter: R.J. Gale, Texas Instruments
Authors: R.J. Gale, Texas Instruments
R. Kraft, Texas Instruments
R.T. Laaksonen, Texas Instruments
A.L.P. Rotondaro, Texas Instruments
Correspondent: Click to Email
As device dimensions continue to shrink to 0.18um and below, the interaction between steps in a process flow becomes more critical. These interactions can be synergistic. In many cases, however, the processes must be co-optimized to minimize the negative effects. One of the most critical process modules in a CMOS device flow is the formation of the gate geometry. We will focus on pattern, etch, and post-etch clean interactions in forming the gate. Dry etch is used to reduce the photoresist patterned line width. This approach permits the wafer patterning to be performed in a more robust process regime thus producing less variation. Once the desired line width reduction has been accomplished, the polysilicon is dry etched, stopping on the thin (<30A) gate oxide. Finally, the remaining photoresist and etch polymer residues must be removed without stripping the thin gate oxide protecting the active regions of the device. Changes in the dry etch process to maximize anisotropy to provide vertical profiles for the gate geometry and high selectivity to gate oxide drive a more aggressive post etch clean process that also must be optimized for oxide selectivity and critical dimension control. This paper discusses the challenges and tradeoffs to successfully accomplish the 0.18um gate formation.