AVS 45th International Symposium
    Electronic Materials and Processing Division Thursday Sessions
       Session EM+PS-ThM

Paper EM+PS-ThM5
Structural Properties of Ultrathin Films of High Dielectric Constant Materials on Silicon

Thursday, November 5, 1998, 9:40 am, Room 314/315

Session: Processing of High K Dielectrics for DRAMs
Presenter: E. Garfunkel, Rutgers University
Authors: E. Gusev, IBM T.J. Watson Research Center
H.C. Lu, Rutgers University
T. Gustafsson, Rutgers University
E. Garfunkel, Rutgers University
G.B. Alers, Bell Laboratories, Lucent Technologies
Correspondent: Click to Email
The high tunneling rates in ultrathin gate oxides is driving the search for higher-K replacement dielectrics in silicon microelectronics. Ta@sub 2@O@sub 5@ and several other metal oxides are now attracting the attention of the device community. One problem that plagues the use of metal oxides on Si is the formation of an interfacial SiO@sub 2@ layer; such layers limit the capacitance and can degrade the electrical properties of the gate structures. We have examined the composition of interfacial layers of several high dielectric constant oxide systems using high resolution medium ion energy scattering. We find that the interfacial region is best described as neither Si/SiO@sub 2@/metal-oxide nor Si/metal-oxide, but can be viewed as a compositionally graded oxide with a dielectric constant significantly higher than that of pure SiO@sub 2@ (as inferred from electrical measurements). Annealing changes the near-interfacial composition substantially. When post anneal temperatures are kept low, stable composite oxide structures (with physical thickness greater than 7nm) can be obtained that demonstrate good electrical properties and an effective SiO@sub 2@ thickness of less than 2 nm.