Paper EM-WeM11
Electrical Characterization and Localized Density of States Extraction of Thin-Film Transistors Based on Sol-Gel Derived ZnO Channel Layers with Different Annealing Temperatures

Wednesday, November 1, 2017, 11:20 am, Room 14

We report on the fabrication and electrical characterization of bottom gate thin-film transistors (TFTs) based on sol-gel derived ZnO channel layer. The effect of annealing of ZnO active channel layers on electrical characteristics of the ZnO TFTs was systematically investigated. Photoluminescence (PL) spectra indicate that the crystal quality of the ZnO improves with increasing annealing temperature. Both the device turn-on voltage (V_on) and threshold voltage (V_T) shift to a positive voltage with increasing annealing temperature. As annealing temperature is increased, both the subthreshold slope (SS) and the interfacial defect density (D_it) decrease. The field effect mobility (μ_FET) increases with annealing temperature, peaking at 800 ℃ and decreases upon further temperature increase. Besides that, the temperature dependent field effect measurement (from 296 K to 330 K) was used to gain an insight on the annealing temperature effect on sol-gel derived ZnO TFTs electrical characteristics. The conduction processes in these TFTs are thermally activated and the drain current, especially in subthreshold regime, obeys Arrhenius equation. Thermal activation energy and a corresponding prefactor parameter were extracted from temperature dependent field effect measurement. The Meyer-Neldel (MN) rule widely observed in the intrinsic material property study is also obeyed by the relation between thermal activation energy and the prefactor parameter. By combing the MN rule and applying the self-consistent procedure, the localized sub-gap density of states ( DOSs) of different temperature annealed sol-gel derived ZnO TFTs were successfully extracted. The DOSs for subthreshold regime decrease from 10¹⁹ eV^-1cm^-3 level to 10¹⁷ eV^-1cm^-3 level with increasing annealing temperature from 600 ℃ to 800 ℃ and no substantial change was observed with further temperature increase to 900 ℃. The results show that DOSs decrease with annealing temperature increase in general, but annealing at a very high temperature may not be beneficial to reducing DOSs. It was found that the TFTs with ZnO layers annealed at 800 °C for one hour shows the best electrical performance with the highest field effect mobility and lowest localized DOSs.