AVS 62nd International Symposium & Exhibition
    Selective Deposition as an Enabler of Self-Alignment Focus Topic Thursday Sessions
       Session SD+AS+EM-ThM

Invited Paper SD+AS+EM-ThM3
Selective Deposition of Copper-Manganese Alloy for Interconnects

Thursday, October 22, 2015, 8:40 am, Room 210F

Session: Fundamentals of Selective Deposition
Presenter: Roy Gordon, Harvard University
Correspondent: Click to Email
As copper interconnections are made smaller, they fail more easily by electromigration. The dominant pathway for motion of Cu atoms is along the interfaces between Cu and the surrounding insulator surfaces. In current technology, a tantalum nitride diffusion barrier and a Ta or Co adhesion layer are placed between Cu and the insulators. Because these layers are more resistive than Cu, the composite interconnect line has a higher resistance than one that would consist entirely of pure Cu. Here we describe how selective placement of manganese within the insulator surface can provide the necessary stabilization, adhesion and barrier properties for Cu lines without the resistance penalty of TaN/(Ta or Co) layers. After trenches and vias are etched into the insulator, CVD is first used to deposit a thin layer of manganese nitride conformally on all exposed surfaces of the insulator as well as on the Cu exposed at the bottoms of the vias. Then less than a monolayer of iodine is chemisorbed onto the MnNx from ethyl iodide vapor. Next, this iodine catalyzes selective, bottom-up CVD of Cu-Mn alloy so that it fills even the narrowest trenches and vias without any voids or seams at the centerlines. The iodine “floats” on the growing surface of the Cu, and is finally removed by chemical-mechanical polishing along with the Cu-Mn overburden and the MnNx on top of the insulator. During subsequent anneals, Mn rapidly diffuses out from the MnNx and from the Cu-Mn alloy into the near-surface regions of the insulator to form an insulating layer of MnSixOyNz surrounding the Cu. The necessary Cu adhesion and barrier properties are provided by this insulating layer of MnSixOyNz selectively placed just inside the surfaces of the insulators. During anneals, Mn and nitrogen originally located on the Cu surfaces at the bottoms of vias disappear as the Mn and N are re-distributed by diffusion to nearby insulator surfaces. The result is direct, low-resistance connection between Cu in vias with Cu in the metallization level below. This selective migration of Mn leaves pure, low-resistance Cu completely filling the entire volume of trenches and vias, providing the lowest possible line resistance. Thus Mn is placed selectively only where it is required to increase adhesion and lifetime before failure by electromigration, to prevent diffusion of Cu into the insulator and to avoid corrosion of Cu by water or oxygen. The same sequence of process steps can apply Cu to the walls of through-silicon-vias to conduct signals from one chip to another. This process can also form Cu seed layers for electrodeposition of Cu-filled vias for distributing power through silicon chips.