Invited Paper PS2-TuA9
Feature Scale Modeling of Semiconductor Processes

Tuesday, October 20, 2015, 5:00 pm, Room 210B

An overview of monte carlo feature scale modeling work will be presented. The two major areas of discussion will be etching and metallization processes.

In high aspect ratio (HAR) oxide etch processes the mask gates the amount of etchants and passivants entering the feature and has a large influence on the resulting etched profile. Mask sidewall slopes alter the path of ions entering the feature thereby modifying the ion strike map inside the feature. Mask geometry also influences polymer deposition within mask and bow formation in oxide. Mechanisms for off-axis profiles and profile distortion include: off-axis ion incidence to wafer, non-uniform polymer deposition at opening, re-deposition of etch byproducts, feature geometry (mask), mask reflow, charging in feature, and off-angle yield curve peaks. Two cases illustrate the interplay of these profile distortion mechanisms: pattern distortion dependence on etch stop layer charging properties, and the influence of a tilted hard mask on HAR trench oxide etch profile. Feature scale models can be used to study integration issues in multi-step processes. A thirteen step spacer double patterning integration has been studied showing the importance of the spacer etch step. An STT-MRAM (Spin Transfer Torque - Magnetoresistive Random Access Memory) etch process will be discussed. Removal of metal sidewall deposits resulting from re-deposition of sputtered MTJ metal layers is a major issue. The study looks at ion beam etching.

The metallization topics reviewed will inlcude copper physical vapor deposition (PVD) in dual-damascene (DD) features, predicting across wafer coverage in feature, and copper reflow studies. In DD features a sloped inner via sidewall can have faster yields than the trench bottom. With reactor models supplying across wafer flux and aedfs it is possible to predict feature coverage properties as a function of wafer position. With smaller feature sizes copper reflow is being explored as a means to fill via and trench structures for back end of line interconnects. Using a simple hopping surface diffusion model, reflow behavior is shown. The model predicts the initial reflow causes rounding of the Cu surfaces and a shrinking of the opening as the surfaces round to a more minimal surface configuration.