| AVS 62nd International Symposium & Exhibition | |
| Plasma Science and Technology | Tuesday Sessions |
| Session PS1-TuA |
| Session: | Novel Materials and Etch Chemistry |
| Presenter: | Dunja Radisic, IMEC, Belgium |
| Authors: | D. Radisic, IMEC, Belgium L. Souriau, IMEC, Belgium V. Paraschiv, SC Etch Technology Solutions D. Goossens, IMEC, Belgium F. Yamashita, Tokyo Electron Miyagi Limited, Japan N. Koizumi, Tokyo Electron Miyagi Limited, Japan S. Tahara, Tokyo Electron Miyagi Limited, Japan E. Nishimura, Tokyo Electron Miyagi Limited, Japan W. Kim, IMEC, Belgium G. Donadio, IMEC, Belgium D. Crotti, IMEC, Belgium J. Swerts, IMEC, Belgium S. Mertens, IMEC, Belgium T. Lin, IMEC, Belgium S. Couet, IMEC, Belgium D. Piumi, IMEC, Belgium GS. Kar, IMEC, Belgium A. Furnemont, IMEC, Belgium |
| Correspondent: | Click to Email |
The short- and damage-free patterning still remains the major challenge for the STT-MRAM high-volume commercialization. High-volume reactive ion etching (RIE) based short- and damage- free magnetic tunnel junction (MTJ) patterning was developed and electrically tested for isolated devices of sizes starting from 200nm down to 75nm and below. There was a tight TMR distribution measured after patterning (standard deviation of 7-14% was achieved) indicating that the process was short-free and it had no detrimental effect on the stack magnetic performance. In addition, measured TMR showed no significant size dependence, i.e., the TMR value was in the same, constricted range, for devices of different sizes. The process yield was 100%, meaning that all of the measured devices were functional and fitting the narrow TMR distribution.
The basic patterning sequence consisted of noble gas-based dry etch in RIE reactor followed by an in-situ SiN encapsulation in the RLSA reactor (both from Tokyo Electron Limited). MTJ stack was CoPt-based bottom pin with perpendicular anisotropy. Either TiN or Ta was used as a hard mask for etching. The stack was partially etched using medium bias process which resulted in some metallic re-deposition on the sidewalls. The remaining stack was etched and the sidewall residues efficiently removed using the high bias process step. For both steps, only noble gasses were used, so that the damage by reactive plasma species was prevented. The device performance dependency on the temperature in RIE reactor was studied by using either -20ºC or 60ºC ESC. The effect of the post-etch oxidation, aimed to convert possible metallic remains on the sidewalls into non-conductive metal oxides, was also tested. The in-situ SiN encapsulation was applied after etching to prevent possible stack properties modifications due to interaction with the atmosphere. The in-situ etch and deposition capability allowed for patterning sequences where multiple etching and deposition steps were combined. The approach with whole stack etch followed by encapsulation, as well as the approach with partial stack etch (down to MgO), followed by SiN spacer formation, remaining stack etch and final SiN encapsulation were used. In the second case, the SiN spacer formed after etching stopping in MgO was intended to act as a dielectric medium preventing the shorts caused by re-deposition.
The best device performance was achieved by using Ta HM, approach with partial etching stopping in MgO, spacer formation, followed by the remaining stack etching and final encapsulation. The oxidation steps were applied after etch stopping in MgO, and after etching of remaining MTJ stack.