Invited Paper PS-MoM1
FEOL Patterning Challenges for Sub 14nm FDSOI Technology

Monday, October 19, 2015, 8:20 am, Room 210B

Fully-depleted SOI devices (FDSOI) are proven to provide excellent control of gate electrostatics. This makes them a real solution to meet performance requirements down to 10nm technology node, however new architectures such as stacked silicon nanowires will be required to maintain low leakage current when further downscaling gate length. Additionally new materials are required to build transistor channel complying with ON-state current expectations, such as new channel materials such as germanium or compound semiconductors or low k materials at the spacer level.

These changes in transistor integration raise quite a number of new challenges for etching and stripping in that they introduce new materials with uncommon properties compared to usual silicon-based devices.

Another challenging aspect of device downscaling is the enhanced demand for high-selectivity etch. In spacer definition for instance, maximum allowable silicon recess in source / drain regions is less than 0.5nm for the 14nm node. To this end new techniques are being developed that involve a prior modification of the etched layer down to a controlled depth, followed by the removal of the modified layer selectively to the non-modified material.

On the technology side, immersion 193nm lithography has reached its limits in resolution and the most critical levels require costly dual or quad-patterning technique to achieve stringent CD specifications in current 14nm and beyond. Solutions to further expand 193nm lithography capabilities at lower costs are showing promising results, such as sidewall image transfer (SIT) or directed self-assembly (DSA). Nevertheless these newly developed techniques involve process adaptations on the plasma etching side since they induce changes in the masking materials.