Paper PS+SS+TF-WeM4
Self-Limited Ion Implantation for Precise Low-k Spacer Etching

Wednesday, October 21, 2015, 9:00 am, Room 210A

With aggressive device shrinking, parasitic capacitances through the spacer become a greater contributor to the total device capacitance. This issue is exacerbated by the common use of SiN spacers. Since SiN has a relatively large dielectric constant (k~7.5), a simple approach to reduce capacitive coupling through the spacer is to supplant it with a low-k material [1]. Therefore, the reduction of spacer k value is a key for the high performance devices. In this context, Low-k films like SiCO, SiOCN or SiBCN have been proposed for the C014 technology node to replace the traditional silicon nitride investigated.

Today, the Low-k spacer etching is considered as one of the most challenging step in the high performance FDSOI devices realization. A trade-off has to be found between silicon germanium (or silicon) recess, foot formation and CD control impacting the device performances. The etch process must also be compatible with epitaxial step.

In a recent study, we proposed a new etch approach [2] for silicon nitride spacer etching. This new etching process is based on a Self-Limited Ion Implantation by plasma. In a first step, the film is modified in volume by a Hydrogen plasma performed in a conventional etch tool (CCP or ICP) followed in a second step by a 1%HF wet cleaning to remove the modified layer selectively to the non-modified material. We demonstrated that the silicon germanium recess was estimated to less than 6A with no foot formation, while a silicon germanium has grown by epitaxy without defects [2].

In this study, we propose to evaluate the compatibility of this new etch approach with low-k films like SiCO or SiCBN. By playing on plasma operating conditions performed in ICP etch tool, we will demonstrate that the Low-k films can accurately be etched with atomic layer control, stopping on SiGe or Si. The key parameters for such etch precision are identified as H ion energy and H ion dose implanted in the low-k film. The etch mechanisms to remove the modified layer by wet cleaning process will be understood on blanket wafers thanks to XPS and infrared spectroscopy analyses.

Finally the compatibility of this new Low-k spacer etching process with the epitaxial step will also be presented for C014 FDSOI integration.

References

[1] H. Niebojewski, C. Le Royer, Y. Morand, M-A. Jaud, O. Rozeau, E. Dubois, T. Poiroux, “ Extra-low Parasitic Gate-to-Contacts Capacitance Architecture for sub-14nm Transistor Nodes”, IEEE Euro SOI conference, 2013