Invited Paper EM+NS+PS-MoA3
Harnessing Chemistry to deliver Materials and Process for theNext 10 Years of CMOS Evolution

Monday, October 19, 2015, 3:00 pm, Room 210E

Harnessing Chemistry to Deliver Materials and Processes for the Next 10 Years of CMOS Evolution

Robert Clark

TEL Technology Center, America, LLC

Albany, NY 12203

Robert.clark@us.tel.com

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The continued scaling of the Integrated Circuits (ICs) according to Moore’s law has led to a doubling of the number of devices per unit area in semiconductor microchips approximately every 2 years since 1962. Over the past decade traditional scaling by simple linear shrinking has effectively ceased as IC makers have adopted new 3-dimensional device structures, complex integration schemes and new processes and materials for an expanding number of applications in order to overcome fundamental physical limits. In order to continue Moore’s law in the coming decade this trend will not only continue, but intensify as devices are scaled to a level approaching atomic dimensions. Broadly speaking, two major trends are influencing the development of future IC manufacturing processes: the need to harness the third dimension to extend Moore’s law; and the need for “self-something” processes. “Self-something” processes refers to processes or schemes that are directed chemically to attain a desired result and includes processes that are self-limited (e.g. ALD or ALE), self-directed (e.g. directed self-assembly or selective deposition), or self-aligned (e.g. self-aligned contacts) in some way that enables device density scaling. “Self-something” processes are required in order to harness the third dimension and make use of new non-planar device architectures (e.g. FinFETs and DRAM capacitors), device arrays/stacking (e.g. 3D NAND and cross-point memory), and 3D integration (e.g. monolithic 3D, and chip stacking). Highly tailored ALD processes are being investigated to fabricate functional material layers. Interspersed treatments and doping may be used to modify the physical and electrical properties of ALD films further in order to optimize the resulting physical or electrical properties. To improve device contacts, ultra-thin dielectric and metal layers may be deposited inside of high aspect ratio contact structures in order to provide lower contact resistivity. Selective deposition processes can be used to deposit functional materials only where they are needed, thus reducing the patterning burden during IC manufacturing. Depositing dopant layers by ALD for thermal solid source doping can be used to conformally dope 3-D device structures without the damage caused by implantation. Examples of these and similar processes will be described and discussed along with the chemical processes and transformations governing film deposition, composition, structure, and interface control.