| AVS 62nd International Symposium & Exhibition | |
| Electronic Materials and Processing | Thursday Sessions |
| Session EM+MS-ThM |
| Session: | III-N Nitrides for Optoelectronic Applications |
| Presenter: | Shalini Gupta, Northrop Grumman ES |
| Authors: | S. Gupta, Northrop Grumman ES R. Howell, Northrop Grumman ES E. Stewart, Northrop Grumman ES J. Parke, Northrop Grumman ES B. Nechay, Northrop Grumman ES M. King, Northrop Grumman ES H. Cramer, Northrop Grumman ES J. Hartman, Northrop Grumman ES R. Freitag, Northrop Grumman ES M. Snook, Northrop Grumman ES I. Wathuthanthri, Northrop Grumman ES G. Henry, Northrop Grumman ES K. Renaldo, Northrop Grumman ES |
| Correspondent: | Click to Email |
Northrop Grumman Electronic Systems (NGES) reports on the development of a novel field effect transistor structure, based on a super-lattice epitaxial layer combined with a three dimensional castellated gate structure to achieve a 3x improvement in RF switch figure of merit compared to current state of the art transistor technologies. RF switch components are vital for the successful implementation of a variety of system architectures, spanning applications from phased array radars to the wireless components of mobile phones and consumer electronics.
NGES used MOCVD growth techniques to grow a GaN/AlGaN based super-lattice on a 100 mm diameter semi-insulating SiC substrate which is used as the SLCFET conductive channel. This super-lattice creates multiple 2DEGs producing parallel current channels between the source and drain of the device resulting in currents several times higher than conventional FETs and a record low GaN epi sheet resistance of 60 ohm/sq. The low epi sheet resistance in turn reduces the on resistance of the FET which results in a low insertion loss RF switch. Although super-lattice structures have been employed to make optoelectronic semiconductor devices, their use in FETs have been limited due to difficulty in pinching-off the stacked paralleled current channels. This is because the top channels screen the bottom channels from the electric field of the gate thereby increasing the voltage needed to pinch off the channel and turn off the device to a value beyond the breakdown field of the semiconductor. The SLCFET overcomes this challenge by employing a side-pinching gate. This is realized by etching features in the semiconductor prior to a 0.25 um gate deposition which allows the gate metal to surround the channels on the top and sides. This feature resembles the crenellations of a castle and hence is called a castellated gate.
Electrical measurements of the SLCFET transistor reveal a high IMAX of 2.7 A/mm and a pinch off voltage of -8V. The SLCFET has a low on resistance (RON) of 0.4 Ohm-mm and an off capacitance (COFF) of 0.2 pF/mm, resulting in an RF switch figure of merit (Fco = 1/2πRONCOFF) of 2 THz, 3x higher than the current state of the art FET based RF switches. SLCFET MMICs have been designed and tested including Single Pole Double Throw (SPDT) switches, tunable filters, and true time delay units. State of the art electrical results have been obtained, such as a series-shunt broadband (1-18 GHz) SLCFET SPDT with a measured insertion loss of 0.25 dB at 10 GHz, with -35 dB of isolation and -23 dB of return loss. These state-of-the-art results demonstrate that SLCFET is an enabling technology for next generation RF systems.