AVS 61st International Symposium & Exhibition
    Selective Deposition as an Enabler of Self-Alignment Focus Topic Wednesday Sessions
       Session SD-WeA

Paper SD-WeA11
Growth and Characterization of Ultra-Thin Silicon Dioxide Layers for Low-k Dielectrics on HOPG and Graphene

Wednesday, November 12, 2014, 5:40 pm, Room 318

Session: Process Development for Selective Deposition and Self-Aligned Patterning
Presenter: Antonio Lucero, University of Texas at Dallas
Authors: A. Lucero, University of Texas at Dallas
L. Cheng, University of Texas at Dallas
Y.G. Lee, University of Texas at Dallas
HH. Hwang, University of Texas at Dallas
X. Qin, University of Texas at Dallas
R.M. Wallace, University of Texas at Dallas
J.Y. Kim, University of Texas at Dallas
Correspondent: Click to Email

Despite graphene’s excellent electrical properties, little progress has been made in developing a successful, high performance logic device due to the difficulty of creating a band gap. A proposed device which side steps this issue is the graphene bilayer pseudo-spin field effect transistor (BiSFET)[1]. It has been suggested that a low-k, ultra-thin (<3 nm) tunneling dielectric is needed for the operation of the BiSFET. The inert surface of graphene presents challenges for the scaling that is necessary to grow this ultra-thin layer. This work focuses on the development of a SiO2 deposition process which can be used as a low-k tunneling barrier. Additionally, we investigate the inclusion self-assembling monolayers (SAM) to further reduce the dielectric constant. To this aim, two growth techniques well-known for their thin film growth capabilities are compared: molecular beam epitaxy (MBE) and atomic layer deposition (ALD).

Growth using MBE and ALD is studied on both highly ordered pyrolytic graphite (HOPG) and transferred graphene. For MBE growth, silicon deposition is carried out in a UHV cluster tool and the films are subsequently oxidized to form SiO2. Film growth has been scaled from 3 to 1 nm in thickness while maintaining uniform coverage. The ALD process uses tris(dimethylamino)silane and ozone at room temperature for growth. In-situ static ozone treatment is used to encourage nucleation similar to previous work [2]. The static ozone cycle is repeated from 3 to 10 times in order to study the scalability of the process. Thickness varies from 2 to ~1 nm, depending on the number of cycles. Growth rate is calculated using x-ray photoelectron spectroscopy (XPS) attenuation of substrate peaks and confirmed with transmission electron microscope. Surface morphology is intensively studied using an atomic force microscope (AFM) to ensure films are continuous and uniform. Morphology for MBE and ALD films is good even when scaled to 1 nm. Raman spectroscopy confirms that no significant defects form during the growth process. Metal-insulator-metal (MIM) capacitors are fabricated in order to evaluate the effectiveness of the ultra-thin silicon dioxide films as tunneling dielectrics both as-is and with octadecyltrichlorosilane SAM functionalization. Results indicate that both MBE and ALD SiO2 are effective tunneling dielectrics with and without OTS.

We would like to thank the Toshiba Mitsubishi-Electric Industrial Systems Corporation (TMEIC) for providing the ozone generator used in this study and SWAN for their financial support.

References:

[1] S. K. Banerjee, et al., Electron Device Lett. 30, 158 (2009).

[2] S. Jandhyala, et al., ACS Nano, 6, 2272 (2012)