AVS 61st International Symposium & Exhibition
    Selective Deposition as an Enabler of Self-Alignment Focus Topic Wednesday Sessions
       Session SD-WeA

Invited Paper SD-WeA1
Material Requirements for Self-Aligned Patterning – a Lithographer’s Perspective

Wednesday, November 12, 2014, 2:20 pm, Room 318

Session: Process Development for Selective Deposition and Self-Aligned Patterning
Presenter: Charles Wallace, Intel Corporation
Correspondent: Click to Email
As feature sizes shrink in semiconductor processes, overlay control is quickly becoming the most significant source of variation. Physical limitations of lithography equipment are constantly pushed beyond their capability in order to meet device requirements. This presentation will discuss past, current and future methods of decreasing overlay and critical dimension errors using self-alignment and selectivity. Self-aligned processes in logic-product manufacturing reduce edge-placement-errors (EPE) which improve yield and device performance. Self-aligned VIAs, self-aligned double patterning (SADP) and directed self-assembly (DSA) are some recent examples of complementary patterning techniques to conventional lithography. These processes enable scaling beyond the resolution limits of conventional lithography. In addition to addressing fundamental physical limitations of optical lithography, these techniques can help to reduce costs because of shorter patterning process flows and the use less expensive equipment. Now is the time for material design and selectivity (selective etch, deposition and removal) to start playing a major role in patterning in order to reduce and eliminate overlay error.