AVS 61st International Symposium & Exhibition
    Nanometer-scale Science and Technology Tuesday Sessions
       Session NS+HI-TuM

Paper NS+HI-TuM3
Cut Patterning Challenges for the 14nm-Node and Beyond

Tuesday, November 11, 2014, 8:40 am, Room 304

Session: Nanopatterning and Nanolithography 
Presenter: Ryan Jung, IBM Albany Nanotech Center
Authors: R. Jung, IBM Albany Nanotech Center
J.R. Sporre, IBM Albany Nanotech Center
F.L. Lie, IBM Albany Nanotech Center
S. Kanakasabapathy, IBM Albany Nanotech Center
S. Sieg, IBM Albany Nanotech Center
A. Ranjan, TEL Technology Center, America, LLC
S. Voronin, TEL Technology Center, America, LLC
A. Raley, TEL Technology Center, America, LLC
V. Rastogi, TEL Technology Center, America, LLC
A. Ko, TEL Technology Center, America, LLC
D. Lee, Samsung Electronics
Correspondent: Click to Email
In order to satisfy certain device architecture, fabrication of certain levels such as channel and gate is typically done by first forming line and space arrays, followed by removing or cutting some lines or parts of lines to form the final pattern. For instance, the method of Sidewall Image Transfer (SIT) patterning generates pairs of lines that are structurally connected at the line ends. Accordingly, the line/space patterning must be supplemented with a companion cut mask pattern to remove these undesired features. The cut mask, in addition to removing undesired features, also facilitates orthogonal line end control and dense array tip-to-tip control, such as in memory device, that cannot be achieved solely from lithography side using mask optical proximity control (OPC) and negative tone developed resist. With channel and gate pitch being scaled down to below 80nm, the ability to precisely place the cut mask edge and to control the line end taper angle has a direct impact on defectivity and yield. The ability to control the critical dimension of the cut opening has a direct impact on the tip-to-tip CD and device density. This paper evaluates the advantages, technical challenges, and extendibility of various cut schemes for 14nm node and beyond, focusing on line edge profile and tip-to-tip control. This work was performed by the Research and Development Alliance Teams at various IBM Research and Development Facilities