Paper TF+AS+EM+NS+SS-ThM11
Studies of Electrical and Surface Properties of High-k Dielectric Gate formed by Al₂O₃, HfO₂, Al_xHf_yO_z and AlHfON on Silicon via Atomic Layer Deposition

Thursday, October 31, 2013, 11:20 am, Room 104 A

In order to meet the increasing demand for high frequency electronic devices, the physical dimensions of MOSFETs have been continuously scaled down to nanoscale. However, one of the bottlenecks we encountered during the down-scaling process is the tunneling current leakage at gates. SiO₂, the most commonly used traditional gate dielectric experiences an appreciable amount of tunneling current when gate thickness is below 1-1.2 nm. The leakage greatly degrades the performance of nanoelectronics. Therefore, we propose using high-k dielectrics to replace SiO₂, which can effectively limit the tunneling leakage without losing the current control at gates. Our research has mainly focus on Al₂O₃, HfO₂ and Al_xHf_yO_z deposit on silicon via Atomic Layer Deposition. The Aluminum to Hafnium ratio in the oxide is tuned to maximize the electrical and physical properties of the film. We expect Al_xHf_yO_z to have a better interface than HfO₂ and an intermediate band-gap between Al₂O₃ and HfO₂, as well as better thermal stability. The electrical properties of each oxide will be characterized by fabricating transistors with gate oxide thicknesses of 5, 10, and 15 nm. In addition to the C-V and I-V measurements for capacitors and transistors, the films will be characterized by XPS, AFM, and spectroscopic ellipsometry. To improve the electrical property of the film, we will incorporate N into the high-dielectric films using Plasma ALD. Finally, the effects of various annealing and deposition temperatures at the silicon-oxide interface will be studied using TEM.