Paper MS+AS+EL+EM+PS+TF-TuA9
Advanced Gate Patterning Techniques for 14nm Node and Beyond

Tuesday, October 29, 2013, 4:40 pm, Room 202 B

For advanced CMOS nodes, traditional patterning processes are challenged to meet the technology needs of certain key levels. For example, conventional 193nm immersion lithography is not able to resolve features below 40nm half pitch with a single exposure without severe design rule restrictions. Until further wavelength scaling through Extreme Ultraviolet (EUV) has matured, the industry’s attention is focused on advanced patterning schemes such as Pitch Splitting (PS) Lithography and Sidewall Image Transfer (SIT). In PS, a pattern is defined by two lithography exposure with a certain coordinate shift between the two exposures. PS can be achieved through either litho-etch-litho-etch or litho-litho-etch. In SIT, a pattern is defined by creating a mandrel in one lithography exposure, depositing a conformal spacer film on the mandrel, and pulling out the mandrel, resulting in two standing spacer for the pattern frequency doubling. This work evaluated the advantages and technical challenges of PS and SIT patterning schemes for line-space application. We will focus on CD uniformity improvement, line edge/line width roughness control, pitch walk control, and the extendability of each technique. RIE challenges common to double patterning such as through pitch etch bias will also be discussed.

This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities and in joint development with TEL Technology Center, America, LLC