AVS 60th International Symposium and Exhibition
    Electronic Materials and Processing Tuesday Sessions
       Session EM+MI+NS+SS+TF-TuA

Invited Paper EM+MI+NS+SS+TF-TuA11
Resistive Switching Random Access Memory (RRAM) - Materials, Device, Scaling, and Array Design

Tuesday, October 29, 2013, 5:20 pm, Room 101 B

Session: High-k Oxides for MOSFETs and Memory Devices II/Oxides and Dielectrics for Novel Devices and Ultra-dense Memory I
Presenter: Y. Wu, Stanford University
Authors: Y. Wu, Stanford University
S. Yu, Stanford University
H.-Y. Chen, Stanford University
J. Liang, Stanford University
Z. Jiang, Stanford University
H-.S.P. Wong, Stanford University
Correspondent: Click to Email

In this paper, we review our recent progress on resistive switching metal oxide memory (RRAM). We continue to explore the stochastic nature of resistive switching in metal oxide RRAM using the Kinetic Monte Carlo method. By including multiple conduction mechanisms, local field and local temperature profile, we substantially improved our stochastic model and studied the RRAM characteristics such as set/forming current overshoot, endurance and retention [1-3]. From an experimental perspective, we have demonstrated that HfOx-based RRAM devices can scale down to less than 10 nm diameter using electron beam lithography (e-beam) and atomic layered deposition (ALD) methods. The devices can switch more 108 cycles with fast speed (~10 ns), large resistance window (~100X), multi-level storage capabilities, and good retention. We also characterized the scaling behavior of the HfOx-based devices such as forming, set/reset voltages [4]. Two-layer stacked HfOx vertical RRAM was fabricated for 3D cross-point architecture. The vertical RRAM devices show excellent performance such as low reset current (<50 uA), fast switching (~50 ns), good endurance (~108 cycles), half-selected immunity (~108 cycles), retention (>105 s @125oC) [5]. Looking into the future, we investigated the impact of wordline/bitline metal wire scaling on the read/write performance, energy consumption, speed and reliability in the cross-point memory array architecture. Possible solutions were suggested to incorporate and mitigate the scaling effects of metal wire interconnect for the next-generation non-volatile memory (NVM) [6-7].

[1] X. Guan, S. Yu, H. -S. P. Wong, IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1172-1182, 2012

[2] S. Yu, X. Guan, H. -S. P. Wong, IEEE Trans. Electron Devices, vol. 59 no. 4, pp. 1183-1189, 2012

[3] S. Yu, X. Guan, and H. -S. P. Wong, International Electron Devices Meeting (IEDM), pp. 585-588, 2012

[4] Z. Zhang, Y. Wu, H.-S.P. Wong, and S. Wong, IEEE Electron Devices Letters, submitted

[5] H.-Y. Chen, S. Yu, B. Gao, P. Huang, J. F. Kang, and H.-S. P. Wong, International Electron Devices Meeting (IEDM), pp. 497-500, 2012

[6] J. Liang, S. Yeh, S.S. Wong, H. -S. P. Wong, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 9, No. 1, Article 9, pp. 9:1 – 9:14, 2013