| AVS 60th International Symposium and Exhibition | |
| Electronic Materials and Processing | Thursday Sessions |
| Session EM+AS+PS+TF-ThM |
| Session: | Materials and Process for Advanced Interconnects I |
| Presenter: | J.M. Torres, Intel Corporation |
| Authors: | J.D. Bielefeld, Intel Corporation M. Chandhok, Intel Corporation J.S. Clarke, Intel Corporation C.J. Jezewski, Intel Corporation K. Singh, Intel Corporation A.M. Myers, Intel Corporation J.M. Torres, Intel Corporation R. Turkot, Intel Corporation |
| Correspondent: | Click to Email |
To lower interconnect signal delay, the industry continues to work on the integration of low-k interlayer dielectrics (ILD). Momentum has slowed in recent years due to the challenges of working with porous thin films. The pores in the ILD can lead to damage and increased roughness during patterning, and can allow precursor penetration during the metal barrier deposition. Low-k ILDs (k~2.0) exhibit 40-50% porosity with interconnected pores with pore size at approximately 2nm+. These challenges are currently reducing interconnect reliability and inhibiting combined capacitance and resistance scaling.
Two approaches have been investigated to mitigate the integration issues with porous dielectrics. The first is pore sealing, in which a non-porous layer is added to the porous ILD’s surface to enhance adhesion and to prevent metal penetration during barrier deposition. The down-side of pore sealing is that it does not address the issue of damage and profile roughness during the patterning process.
The second approach is pore stuffing, in which a sacrificial material is infiltrated into the pores of a fully cured ILD. This process generates a non-porous material with increased mechanical properties. The benefits of a non-porous material are utilized during both patterning and metallization. Once the metallization process is complete the sacrificial material is removed to restore the properties of the low-k ILD.
In this paper, we will discuss the challenges of finding a pore stuffing material that can fill the pores of the ILD, that can remain in place during dual damascene processing and that can be removed low-k ILD post metal deposition. Next we will show step by step how pore stuffing improves trench profiles, enhances resistance to wet cleans damage, and eliminates metal precursor penetration. Finally the successful implementation of this process into a dual damascene process flow will be shown.