AVS 59th Annual International Symposium and Exhibition
    Electronic Materials and Processing Thursday Sessions
       Session EM-ThM

Paper EM-ThM5
Ultra Low-Power (ULP) Current Logic Gates for Subthreshold-Triode Operation

Thursday, November 1, 2012, 9:20 am, Room 009

Session: Processing for Ultra Low Power Electronics + Semiconductor Heterostructures I
Presenter: K. Lam, Chinese University of Hong Kong, Hong Kong Special Administrative Region of China
Authors: K. Lam, Chinese University of Hong Kong, Hong Kong Special Administrative Region of China
T. Mak, Newcastle University, UK
Correspondent: Click to Email
Most logic gates used today are based on voltage-mode ideas, where the two binary states for 0 and 1 are represented using inverted logic on voltages. In carrying out the basic operations for AND and OR on two levels of voltages for 0 and 1, NAND gates and NOR gates are often required by using inverted logic and inverters are commonly used to get the logical computations functionally correct. It is straightforward to construct a NAND gate with two tightly coupled common drain and source N-channel MOSFET transistors. A properly chosen resistor from the supply voltage to the common drain will then realize the NAND function to the two voltage levels with a reasonable margin. For subthreshhold operation with a supply voltage close to the threshold voltage, the gate switching speed is determined by the subthreshold swing.

There are limitations for these voltage-mode logic gates due to the lack of accuracy and inability to work on very small voltage levels less than the threshold voltage for ultra-low power applications. We explore the idea of current logic by making use of small currents at the subthreshold-triode region to overcome some of these limitations. Using current for the binary inputs of 0 and 1, the 2-input current-mode minimum circuit and maximum circuit are investigated to realize the logical functions of OR and AND gates for subthreshold-triode operation. Our previous work reported that in subthreshold-triode operation it is possible to obtain a subthreshold swing which can surpass the theoretical limit of 60 mV/dec at very small gate voltage less than 0.025V for the IMEC 90 nm process. Further simulation is focused on the evaluation of ULP current logic gates constructed using current-mode min-max circuits. A benchmark test on a dynamic programming network for solving transitive closure problem has been performed on using conventional voltage-mode NAND-NOR logic gates. The results will be compared with the proposed current-mode min-max circuits.