1. Introduction

One of the biggest challenges for the VLSI circuits with 22nm-node and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs) and Vth variation. Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper presents novel FinFET process technologies for 22nm-node and beyond.

 2. Vth Tuning

The Vth of the FinFET is determined by the gate workfunction (WF). A mid-gap metal gate (MG) such as TiN gives a relatively high Vth (±0.4V) for both n- and pMOS FinFETs. In order to further reduce Vth, we have developed a novel dual MG FinFET integration process by using metal interdiffusion technology. In this work, we selected a Mo (4.95eV) and Ta (4.25eV) combination, and demonstrated the integration of a Ta/Mo gate nMOS and Mo gate pMOS FinFET. A Ta diffuses into the underlying Mo layer, piles up at the metal/dielectric interface. Thus, by depositing Mo on both n- and pMOS and by stacking Ta on only pMOS, dual MG CMOS FinFETs with low Vth (±0.2V) were successfully realized without any MG removal process.

By separating the two gates in the FinFET and using one to control the Vth, we have succeeded in obtaining the great advantage of the post-fabrication flexible Vth controllability. The fabricated independent double-gate FinFET (called 4T-FinFET) enabled Vth to flexibly range from around 0.2V to 0.4V.

 3. Vth Variation

So far we have investigated FinFET performance variability for undoped channels with TiN MG. By evaluating the influence of channel doping, fluctuation of gate length and that of fin thickness, we have also found that gate WF variation (WFV) is the dominant source of Vth variation for the undoped TiN FinFET. We speculated that the WFV originates from randomly aligned TiN on rough sidewall channels due to line edge roughness of the patterned resist mask. Then in order to reduce the WFV, we fabricated FinFETs having smooth sidewall channels formed by using orientation-dependent nanowet etching. It was found that σVth’s for the wet-etched case is significantly lower than that for the dry-etched case. This means that the smooth sidewall channels formed by using the nanowet etching well contribute to the reduction of the WFV.

 4. Summary

 By introducing Ta/Mo dual metal gate technology, low Vth (±0.2V) can be obtained for CMOS FinFETs. By separating the DG, Vth can be tuned from 0.2V to 0.4V flexibly. Flattening of Si-fin sidewall channel is very promising for reducing Vth variations.