AVS 58th Annual International Symposium and Exhibition
    Plasma Science and Technology Division Tuesday Sessions
       Session PS-TuM

Paper PS-TuM5
Trench First Metal Hard Mask RIE for the 22 nm Node and Beyond

Tuesday, November 1, 2011, 9:20 am, Room 201

Session: Advanced BEOL / Interconnect Etching I
Presenter: Yannick Feurprier, TEL Technology Center, America, LLC
Authors: Y. Feurprier, TEL Technology Center, America, LLC
R. Gaylord, TEL Technology Center, America, LLC
Y. Chiba, TEL Technology Center, America, LLC
K. Kumar, TEL Technology Center, America, LLC
D. Trickett, TEL Technology Center, America, LLC
Y. Mignot, ST Microelectronics
R. Srivastava, GlobalFoundries
T. Kwon, GlobalFoundries
R. Koshy, GlobalFoundries
C. Labelle, GlobalFoundries
Y.J. Park, Samsung
E. Wormyo, IBM Research
S. Allen, IBM Research
E. Soda, Renesas Electronics
D. Horak, IBM Research
Y. Yin, IBM Research
J. Arnold, IBM Research
M. Ishikawa, Toshiba America Electronic Components
H. Tomizawa, Toshiba America Electronic Components
Correspondent: Click to Email

Trench First metal Hard Mask (TFmHM) integration scheme for BEOL has gained traction over recent years because it can mitigate many challenges that are inherent with Via First Trench Last (VFTL) scheme. This integration scheme was more recently shown to enable Self-Aligned Via (SAV) patterning. The SAV patterning implies a pretty drastic change of the via process as, on top of the usual via requirements, the via patterning process needs to be selective to the metal HM. Key process parameters including temperature, gas chemistry, power and pressure were investigated. The required selectivity of the materials and tight CD control capability necessitate temperature controllable chucks eventually allowing greater process flexibility for both via and trench patterning.
The simultaneous control of via, trench and chamfer profiles (i.e. Critical Dimensions, depth, taper profile, etc), implies the need for better control of the metal HM selectivity during both SAV and trench patterning and the need for flexible adjustment of the ion energy and control of the flux of ions and active neutrals. Low-k material damage control is always pertinent in the RIE process as dimensions get smaller. As the direct result of such tight process guidelines, the hardware challenges arise and new dimensions in process controls are needed.
In this paper, the RIE efforts on process controls of the via and trench profiles, the metal HM selectivity, associated hardware solutions and future process flow options under TFmHM scheme will be discussed.
This work was performed by the Research and Development team at TEL Technology Center America in joint development with IBM Research Alliance Teams in Albany, NY 12203. This work has also been supported by the independent Bulk CMOS and SOI technology development projects at the IBM Microelectronics Div. Semiconductor Research & Development Center, Hopewell Junction, NY 12533.