Paper PS-MoM9
Double Patterning Challenges for the sub 22nm CMOS Nodes

Monday, October 31, 2011, 11:00 am, Room 201

Wavelength and Numerical Aperture scaling in optical lithography have allowed CMOS density scaling to march along the Moore ’s Law curve for the past three decades. However, at the sub 22nm CMOS nodes, the print pitch faces a technological barrier at the 80nm mark for the Front, Middle and Back Ends of Line. Until further wavelength scaling becomes available through Extreme Ultraviolet (EUV), the industry’s attention is focused on Double Patterning. Multiple Interdigitated Lithography and Sidewall Image Transfer (SIT) are the two broad categories of techniques under consideration. Interdigitated Lithography can be subdivided into approaches with and without multiple passes through etch. Both of these techniques present unique etch challenges in assembling looser pitch patterns into a composite mask and subsequent pattern transfer into the stacks of interest. We will review etch perspectives on the applicability of double patterning methods to various levels in the process flow.

In particular, Fins for FinFET technology represent the tightest pitch (approximately 40nm for the technology nodes in development at this time) and yield well to Sidewall Image Transfer. We will present the issues surrounding mandrel definition and spacer film properties for Fin definition. The Gate level poses competing requirements of overlay control between the simpler patterns and the need to attain multiple Critical Dimensions (CDs) and pitches. We will examine this and the challenges of etch into advanced gate stacks for the 14nm node. At the Interconnect levels, we will consider the challenges of transferring not only trenches but also self aligned via patterns at sub -40nm half pitch into ultra low-k (ULK) dielectrics.