Paper PS-MoM10
Novel Etch Mechanism for High Selectivity Etching of Silicon Nitride over Silicon and Silicon Oxide for Spacer Applications

Monday, October 31, 2011, 11:20 am, Room 201

To continue scaling CMOS devices at the traditional pace following Moore’s law, high selectivity of etch processes towards multiple materials is approaching nanoscopic dimensions. The spacer etch process is a very critical element in the CMOS device process flow as it ensures and enables the electrical isolation of source/drain and gate regions. Extremely high precision is needed to form a silicon nitride (SiN) spacer without damaging exposed Si, SiO₂, or other surfaces (SiGe or SiC for example). This process is even more challenging for non-planar devices (such as FinFETs and Trigates), where the plasma process needs to be able to form the spacer on the gate sidewall, but not the fin sidewall. At the same time the exposed SiO₂ and Si surfaces (if applicable) have to withstand the extended processing necessary to form the spacer.

Multiple etch gas chemistries have been evaluated and their impact on etch rates and selectivities for spacer applications have been evaluated. Surface analysis techniques such as XPS and FTIR have been applied in conjunction with OES analysis of the plasma to study the etch mechanisms leading to the observed etch rates. Fundamental differences in etch mechanism were found for different etch gas chemistries.

We observed that during conventional spacer processes, very little difference in plasma polymer deposition onto the respective substrates could be noted. A successful SiN spacer process was rather facilitated by a Si etch process that was selective to SiO₂, where excess oxidation lead to a conversion of Si to SiO₂. This also means that the etch rates of the SiN are limited by the simultaneous oxidation of the same. A potential solution to overcome this limitation would be to control the etch rate by polymer thickness, similar to high selectivity SiO₂ etching. An evaluation of this approach has yielded similar results as the general etch mechanism proposed by Schaepkens et al.[1] [#_ftn1] A novel etch chemistry was also evaluated that enables a different etch mechanism that cannot be described by the general model. The impact of the described mechanisms on actual CMOS devices will be discussed in detail.