Invited Paper PS+MN+TF-TuM5
Wafer Scale Hermetic Packaging of MEMS

Tuesday, November 1, 2011, 9:20 am, Room 202

The explosion of MEMS in automotive and cell phone markets has been enabled by low cost wafer level packaging (WLP) technology that provides a robust and hermetic enclosure for an otherwise delicate device. The more obvious advantage of WLP is greatly improved reliability, because the device is protected from organic and particulate contaminants while in the hands of the end user. A less obvious advantage is the protection provided by WLP during the manufacturing process, which often produces the highest levels of stress that a MEMS device experiences. These processes include wafer grinding, wafer dicing, and chip solder re-flow attachment to circuit boards and other chips. Firstly in this talk, wafer level packaging technologies will be outlined, focusing on the truly hermetic methods -- alloy, glass frit, Au-Au thermo-compression, anodic, and fusion bonding. Secondly the integration of Through Silicon Vias (TSV) with WLP will be discussed. Finally the performance of these technologies will be compared from a manufacturing perspective, including yield and thermal budget.