| AVS 58th Annual International Symposium and Exhibition | |
| Electronic Materials and Processing Division | Monday Sessions |
| Session EM2-MoA |
| Session: | Dielectrics for Ultra Dense Memory Devices |
| Presenter: | Gabriel Molas, CEA Leti Minatec Campus, France |
| Correspondent: | Click to Email |
Charge Trap Memories and 3D Approaches
The standard planar Floating gate Flash memory has been scaled down over 20 years. However, many critical limitations are appearing (charge loss through the top or bottom dielectrics, cell to cell coupling interference, Random Telegraph Noise, reduction of the number of stored electrons, process induced variability…), making difficult further scaling of the memory device.
In this context, charge-trapping memories, based on the TANOS (TaN-Al2O3-Si3N4-SiO2-Si) gate stack, are foreseen as the backbone of future NAND technologies, allowing to reach the 20nm era with planar device structures and to overcome the 1X node when coupled to novel 3D vertical memory architectures. Nevertheless, to face this challenging Flash memory evolution, several process innovations are still required, and an in-depth physical understanding of the gate stack material properties, is needed.
This paper discusses the potentialities and limitations of charge trap memories, and proposes some paths of improvements to fulfil the stringent requirements of future memory generations.
First the engineering of the memory gate stack is investigated. In particular, engineered tunnel dielectrics, alternative charge trapping layers and improved control dielectric stacks are proposed, and their impact on the memory performances and reliability is debated. Experimental results are analyzed by means of models and simulations.
Then in a second part, the integration of charge trap memories in 3D architectures is studied. The various approaches investigated in the literatures are reported, and an original method to process stacked 6nm crystalline nanowires with gate all around SONOS configuration is proposed.