Paper EM-TuA9
Effect of Post Deposition Anneal on the Characteristics of InP MOS Capacitors with High-k Dielectrics
Tuesday, November 1, 2011, 4:40 pm, Room 210
| Session: |
High-k Dielectrics for MOSFETs Part 2 |
| Presenter: |
Rohit Galatage, The University of Texas at Dallas |
| Authors: |
R.V. Galatage, The University of Texas at Dallas
B. Brennan, The University of Texas at Dallas
H. Dong, The University of Texas at Dallas
D.M. Zhernokletov, The University of Texas at Dallas
C.L. Hinkle, The University of Texas at Dallas
R.M. Wallace, The University of Texas at Dallas
E.M. Vogel, The University of Texas at Dallas
|
| Correspondent: |
Click to Email |
Due to high defect density between III-V semiconductors and high-k dielectrics, buried channel structures with InP barrier layers are being considered for CMOS applications1,2. It has been observed that sulfur passivated InP is thermally stable up to ~460° C3. However, little work has been performed to understand the thermal stability of the high-k/InP interface. In this work, the effect of dielectric post deposition anneal (PDA) on InP MOS capacitors with high-k dielectrics was studied. Temperatures above 450° C result in an increase of the interface trap density.
MOS capacitors were fabricated on both n-type and p-type InP substrates with HfO2 and Al2O3 dielectrics. Room temperature ammonium sulfide was used for surface passivation prior to ALD. Various temperatures ranging from 400° C to 500° C were used for PDA and a control sample without any PDA was used. The surface Fermi level is severely pinned for the p-InP substrate4 and the device does not go into accumulation. This behavior is not observed for the n-InP substrate. Room temperature C-V characteristics for HfO2/n-InP devices show increased interface trap response for the samples with PDA above 450° C. However, low temperature (77 K) C-V measurements show that the samples with PDA have similar equivalent oxide thickness (EOT) and their interface trap response can be compared directly. A semi quasi-static method is used to calculate the Dit distribution across the InP band gap. Details of the technique will be presented. The Dit distribution shows a peak located at mid gap for all of the samples which increases with increasing temperature. A similar trend is observed for Al2O3/InP MOS capacitors. Correlation of these results to X-ray photoelectron spectroscopy (XPS) analysis will be presented.
This work is sponsored by SRC FCRP MARCO Materials Structures and Devices Center and the National Science Foundation.
[1] M. Radosavljevic et al., IEDM Tech. Dig., pp.13.1 (2009).
[2] H. Zhao, Y. Chen, J. Yum, Y. Wang, F. Zhou, F. Xue, and J. Lee, Appl.Phys. Lett. 96, 102101(2010)
[3] A nderson, G. W.; Hanf, M. C.; Norton, P. R.; Lu, Z. H.; Graham, M. J., Appl.Phys. Lett, vol.65, no.2, pp.171-173, Jul 1994
[4] Hyoung-Sub Kim, I. Ok, M. Zhang, F. Zhu, S. Park, J. Yum, H. Zhao, Jack C. Lee, and Prashant Majhi, Appl. Phys. Lett. 93, 102906 (2008)