Invited Paper EM-TuA1
High Mobility Channel Materials and Novel Devices for Scaling of Nanoelectronics beyond the Si Roadmap
Tuesday, November 1, 2011, 2:00 pm, Room 210
The introduction of high-k dielectrics and metal gates in advanced CMOS has opened the door to Ge and III-V compounds as potential replacements for Si to further increase the device performance. Using MOCVD the selective area growth of low-defect InP and InGaAs layers in submicron trenches on Si was demonstrated. These virtual Ge-III/V substrates can be processed in a standard CMOS line. Short channel Ge pMOS devices with high drive currents were fabricated. Strain engineering using GeSn source/drain areas allows to boost the performance of these devices so that they can outperform their strained Si counterparts. One of the key problems in developing III/V devices is the near midgap Fermi level pinning associated with the high density of defect states present at the high-k/III-V interface. The origin of these states is still under debate but there are clear indications that there exists a strong relationship with native antisite point defects. Various sulfide and other treatments were investigated to passivate the surface. The measured distribution of interface states and border traps on typical III/V MOS structures has some special consequences on the electrostatic operation of different transistor designs. Since inversion mode devices do not seem to be the appropriate choice for III/V based logic applications, other device types have been explored. The Implant-Free Quantum Well (IF-QW) device enables VLSI-compatible processing by self-aligned source/drain definition. Strained Implant Free Quantum Well Ge-based pFETs show excellent short channel control and record drive currents. The concept was also used to demonstrate high mobility n-channel InGaAs devices. For III/V pMOS devices GaSb is at present the material of choice. Very encouraging results have been obtained on direct heteroepitaxy of GaSb epilayers on InP(001) combined with in-situ deposition of an Al2O3 high-κ gate dielectric. The introduction of these advanced materials also allows the development of new device concepts that can fully exploit the properties of these new materials. Tunnel-FETs, where the III/V material may be either introduced only in the source or in the complete device, can provide superior performance at lower power consumption by virtue of their improved subthreshold behavior, allowing to reduce the supply voltages. Vertical surround gate devices can be produced from III/V nanowires directly grown on silicon, allowing the introduction of a wide range of III/V materials and functionalities on Si. This illustrates some of the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.