| AVS 58th Annual International Symposium and Exhibition | |
| Electronic Materials and Processing Division | Monday Sessions |
| Session EM-MoM |
| Session: | Dielectrics for Novel Devices and Process Integration |
| Presenter: | Mihaela Balseanu, Applied Materials, Inc. |
| Authors: | M. Balseanu, Applied Materials, Inc. L.Q. Xia, Applied Materials, Inc. V. Nguyen, Applied Materials, Inc. M. Naik, Applied Materials, Inc. D. Cui, Applied Materials, Inc. K. Zhou, Applied Materials, Inc. J. Pender, Applied Materials, Inc. B. Mebarki, Applied Materials, Inc. |
| Correspondent: | Click to Email |
The continuous need for films with lower dielectric constant, higher strength, and greater etch resistance drives the need to explore new materials. In this paper we present a study of boron nitride and other boron-based materials for multiple applications in semiconductor devices discussing the benefits and integration challenges.
As critical dimensions shrink and RC delay increases, the dielectric constant of the interconnect is a continuous area of focus. The current silicon carbo-nitride (SiCN) Cu barrier film has a dielectric constant greater than 5.0 and relatively poor step coverage. Significant advances have been made in recent years to develop a low k, conformal and manufacturable BN thin film for Cu barrier applications. The BN film was shown to have improved leakage, mechanical properties and insensitivity to UV cure relative to SiCN.
Back-end of line patterning has increased in complexity with the introduction of ultra-low k (ULK) dielectric materials. Dual hardmask (HM) patterning scheme eliminates the ULK damage caused by photoresist strip process. The TiN HM has faced challenges in extending below 20nm due to post etch residue and high stress leading to line bending. A boron-based HM material was developed to address those integration challenges. The new material has a low and tunable stress eliminating the line bending concerns. Boron content was optimized for the best selectivity to ULK without impacting the film stress. Significant defectivity and queue time improvement was observed with the boron-based HM due to volatility of the etch byproducts. 9% RC reduction relative to the conventional tri-layer patterning scheme was measured using 45nm 2-metal level electrical test structures.
Double or quadruple patterning technique is required for critical dimensions reduction due to the lack of manufacturable EUV lithography. Spacer-based double patterning (SADP) is one of the most adopted process flows to generate one-dimension regular array structures. Its implementation is impacted by the poor step coverage of the conventional PECVD SiN spacer leading to metal line cuts after final polishing step. A low temperature BN film with superior step coverage, minimum pattern loading, good uniformity and low cost was developed for 20nm node and beyond. Its benefit for SADP was verified using a 20nm half pitch logic structure where a 200mm long serpentine yield was improved by 80%.
Evaluation of the boron-based thin films for Cu barrier and patterning applications has shown their potential to replace the conventional materials used today in the logic and memory process flow and thus enabling scaling below 20nm.