AVS 58th Annual International Symposium and Exhibition
    Electronic Materials and Processing Division Monday Sessions
       Session EM-MoM

Invited Paper EM-MoM10
Impact of Vertical Structured Devices for Future Nano LSI

Monday, October 31, 2011, 11:20 am, Room 210

Session: Dielectrics for Novel Devices and Process Integration
Presenter: Tetsuo Endoh, Tohoku University, Japan
Correspondent: Click to Email
For the past thirty years, the device downscaling has been the guiding principle in Si-LSI. The planar MOSFET has supported the expansion of the semiconductor industry; however, recently, the limit of planar MOSFETs is becoming apparent. As the feature size of planar MOSFETs approach the nano generation, it is becoming more difficult to improve its performance by SCE etc. Moreover, the process cost becomes expensive. In order to extend the scalability of CMOS technology to the nano generation; a new device structure is necessary. From above viewpoint, many new structured MOSFETs are proposed. The key points of next generation MOSFET are multi-gate structure, floating body structure and 3D structure. Therefore, proposed Vertical MOSFET [1-2] is emerging as one of the candidate to replace the conventional MOSFET.

In this paper, I will show the excellent performance of Vertical MOSFETs in comparison with others structured MOSFETs from viewpoints of high packing density and large driving current and good gate controllability etc. Moreover, I will show the impact of Vertical MOSFET for high density Memory [3].Next, I will discuss that by using both proposed Vertical MOSFETs[4] and Spin device, Silicon ULSI can be evolved even if becoming in nano generation in forces to Logic. Logic demands new scheme technology for realizing lower power operation and managing the total power consumption. On the other hands, Memory, especially non-volatile memory demands new cell technology for shrinking cell size and realizing high speed programming, low voltage operation and good reliability including endurance. From above viewpoint, we will show the excellent performance of both Logic-in-Memory Architecture [5-7] using MTJ, and MTJ based Vertical structured cell, as follows. First, it is shown that by Logic-in-Memory Architecture using MTJ, a compact LSI with a standby-power-free and immediate-power-up capability can be realized. Next, it is shown that by Vertical structured cell using MTJ, ultra high density non-volatile memory can be realized with utilizing both a capability of Vertical structure MOSFET such as large drive current, excellent gate controllability and compact footprint, and a capability of MTJ such as unlimited endurance and manufacturability integrated in backend metal line of Silicon CMOS technology. Finally, we discuss the impact of spintronic devices for future Nano Si-LSI.

[1] T.Endoh,etal. IECE Trans.EL. E80-C, 1997

[2] T.Endoh,etal. AWAD, 2008

[3] T.Endoh,etal. IEEE IEDM, 2001

[4] T.Endoh,etal. IECE Trans.EL. E92-C, 2009

[5] A.Mochizuki, etal. IEICE Trans.EL E88-A, 2005

[6] S.Matsunaga, etal. APEX 1, no.9, 2008

[7] M.Kamiyanagi,etal. AWAD, 2009