AVS 58th Annual International Symposium and Exhibition
    Electronic Materials and Processing Division Monday Sessions
       Session EM-MoM

Paper EM-MoM1
Surface Cleaning and Monolayer Seeding for ALD of High-k Studied by In Situ STM, STS, and XPS

Monday, October 31, 2011, 8:20 am, Room 210

Session: Dielectrics for Novel Devices and Process Integration
Presenter: Wilhelm Melitz, University of California San Diego
Authors: W. Melitz, University of California San Diego
T. Kent, University of California San Diego
J. Shen, University of California San Diego
A.C. Kummel, University of California San Diego
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Air exposed III-V surfaces nearly always defects which prevent full modulation of the Fermi level thereby impeding their use in practical semiconductor devices such as MOSFETs. For a high speed device, the air induced defects need to be removed to reduce trap states while maintaining an atomically flat surface to minimize interface scattering thereby maintaining a high carrier mobility. For silicon, the only commercial atomic layer deposition (ALD) high-k fabrication process is a replacement gate process to avoid processing induced damage. Surface channel III-V MOS devices can be fabricated with ALD high-K gate-first processes; while ALD is known to greatly reduce surface contaminants, contamination removal is not complete and the order of the surface after ALD cleanup is unknown. Using in-situ scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS) the surface morphology of a multistep process was explored for gate-last unpinning of air exposed InGaAs and InP surface via cleaning with atomic H and ALD nucleating/passivating with trimethyl aluminum (TMA). STM of atomic H cleaned surfaces shows the dosing temperature and a post deposition anneal are critical to forming surfaces that resemble the decapped InGaAs or a highly ordered InP surfaces. For InGaAs(100), 300K H dosing can produce large multilayer etch features which cannot be annealed out; however by dosing at elevated temperatures these features can be avoided. After H cleaning at 380oC, the surface contains dark features consistent with monolayer etch pits, and these features are reduced by a factor ~50 with a post deposition anneal. The H cleaned and annealed surface can be unpinned by a half cycle dose of TMA followed by annealing because it generates an ordered dimethyl aluminum layer providing monolayer nucleation density, and an atomicly flat surface, critical for aggressive EOT scaling. For InP, a low dose of H at similar temperatures and post deposition anneal generates a mixed surface reconstruction; however, with a higher dosing temperature around 440oC and post deposition anneal around 470oC, a single surface reconstruction is observed. A similar atomic H cleaning and TMA dosing procedure has been demonstrated to produced an ordered passivation layer on air exposed InP(100). It has been shown that for InGaAs and InP an oxide free surface can be achieved with atomic H dosing and annealing, however there is a dependence of surface roughness and defect densities on dosing and annealing conditions. The combination of atomic H cleaning and TMA dosing provides a flat ordered surface ideal as a template for ALD of high-k gate dielectrics.