AVS 56th International Symposium & Exhibition
    Thin Film Friday Sessions
       Session TF-FrM

Invited Paper TF-FrM3
Amorphous and Crystalline Metaloxide Semiconductors for Transistor Applications

Friday, November 13, 2009, 9:00 am, Room B4

Session: Transparent Electronic Materials and Applications
Presenter: A. Facchetti, Northwestern University
Correspondent: Click to Email

In this presentation I will discuss our latest results in developing semiconductor metal oxide (SMO) formulations for solution-processed thin-film transistors based on crystalline and amorphous metal metaloxide films. Solution-processed amorphous semiconductor film fabrication by spin-coating and eventually printing is advantageous because of process simplicity, low cost, high reproducibility, chemical composition/stechiometry control, and possible high throughput enabling inexpensive electronics. Regarding crystalline SMO films, In2O3 thin-film transistors (TFTs) were fabricated on various dielectrics [SiO2 and self-assembled nanodielectrics (SANDs)] by spin-coating In2O3 film precursor solutions consisting of methoxyethanol (solvent), ethanolamine (EAA, base), and InCl3 as the In3+ source. Importantly, an optimized film microstructure characterized by the high-mobility In2O3 004 phase, is obtained only within a well-defined base: In3+ molar ratio after annealing at 400 C. The greatest electron mobilities of ~ 44 cm2, for EAA :In3+ molar r atio = 10, V−1s−1, is measured for n+-Si/SAND/In2O3/Au devices. This result combined with the high Ion:Ioff ratios of ~ 106 and very low operating voltages (< 5 V) is encouraging for high-speed applications. We have also developed amorphous Sn-In-O and Zn-Ga-In-O formulations in which the corresponding films can be annealed at far lower temperatures (< 250 ºC). For instance, solution-processed amorphous tin-doped indium oxide (ITO) films for TFT fabrication at temperatures <250 °C can be achieved by controlling film precursor solution In +3 vs. Sn +4 molar ratio resulting in electron mobilities > 2 cm2 V−1s−1 and I on:I off > 10 4 for TFTs using SiO 2 as the gate dielectric. Furthermore, w e demonstrate that hybrid integration of solution-processed ITO semiconductor films SAND enables m ~ 20 cm2 V−1s−1.