Invited Paper PS+MS-MoA6
Logic Etch Challenges at the 22nm Node and Beyond

Monday, November 9, 2009, 3:40 pm, Room A1

Due to increased device integration complexity, there are significant challenges to technology scaling for Logic devices at 22nm and beyond. The issues range from difficulties in scaling device threshold voltage (V_t), and electron and ion mobility enhancements to achieving the proper leakage current for low power devices. Proposed solutions to overcome these challenges include adoption of Metal Gate High-k for threshold voltage and leakage current engineering, to various Strained Silicon techniques to enhance electron and ion mobility, and FinFETs for beyond 22nm technology node. In this presentation, we will review some of challenges associated with front-end logic integration schemes, such as control of Si Recess and Si damage. Si loss and damage after gate etch, spacer etch, and strained Si etch applications can impact source-drain junction depth, and increase device leakage. We will discuss various mechanisms for Si loss and damage, work done by previous authors, what is required at 22nm and beyond, implication for etch and post etch clean, and areas where better understanding is required.