AVS 55th International Symposium & Exhibition
    Manufacturing Science and Technology Monday Sessions
       Session MS+NC-MoM

Paper MS+NC-MoM7
Multi Level “Air Gap” Integration for Advanced Technology Nodes

Monday, October 20, 2008, 10:20 am, Room 311

Session: CMOS Extension and Metrology
Presenter: F. Gaillard, CEA-Leti-MINATEC, France
Authors: F. Gaillard, CEA-Leti-MINATEC, France
D. Bouchu, CEA-Leti-MINATEC, France
R. Gras, STMicroelectronics, France
S. Moreau, CEA-Leti-MINATEC, France
G. Passemard, STMicroelectronics, France
J. Torres, STMicroelectronics, France
Correspondent: Click to Email

In order to extend device’s performance and more particularly to improve interconnects RC delay, crosstalk and power consumption, continuous and innovative materials development have been realised over the twenty five past years to decrease dielectric constant. After the use of fluoride doped silicon oxide, low-k and later on porous ultra low k materials have emerged as serious candidates to isolate copper lines for the 90 - 32 nm nodes. Nowadays, “air cavities” introduction also named “Air Gap” represents the ultimate solution in this classical dielectric material evolution and is an attractive solution to meet the ITRS performance for advanced interconnects (22 nm technology node and below). We present an architecture where a sacrificial SiO2 material deposited on few metal levels (two or more) is further removed by a hydrofluorhydric (HF) chemical etching agent. This HF chemistry diffuses through out patterned apertures localized in a silicon carbide (SiCN) capping layer deposited at the end of the multi level scheme. Thus, full air gaps realization is performed when possible, but SiO2 pillars are still needed on long metal lines patterns to avoid any collapse when complete air cavities are made underneath. This global approach allows air cavities localization, keeps mechanical integrity and avoids any via misalignment issues, as air cavities are introduced at the end of the integration. In this work, we will present a three metal level interconnect realisation achieved at 65 nm design rules on a 300 mm diameter wafer; air cavities will be integrated on two metal levels and further completed up to pads realizations. Associated morphological and electrical results will be discussed. Based on simulation data and supported with experimental results, we have also predicted and demonstrated that an adequate stack composed of different doped or undoped SiO2 materials deposited on the different metal levels can be useful to optimise the SiO2 pillar shape. It consequently improves the coupling capacitance gain on both metal levels, which is directly linked to the air cavities volume. Indeed, if the initial stack is composed of the same SiO2 material, the air cavities present a spherical profile because the HF chemistry removes isotropically the SiO2 layers through the specific apertures. These encouraging “Air Gap” results could represent a promising and low cost solution to move towards the next technology nodes.