Invited Paper MS+NC-MoM3
Challenges and Opportunities for 32nm Node CMOS and Beyond

Monday, October 20, 2008, 9:00 am, Room 311

Future CMOS technologies require significantly more transistors per unit area with improved transistor performance. Gate-length, spacer, and contact scaling are the enablers for increasing transistor density. Scaling these features for future technology nodes is a significant challenge and new processes, materials and integration schemes will be needed. Ultimately new device architectures may be needed to achieve increased density or enhanced performance. Fully depleted SOI devices like Extremely Thin Silicon on Insulator (ETSOI) and FinFETs are the possible choices for alternate architectures. Either option would be a major shift for the semiconductor industry and would pose new challenges compared to conventional planar CMOS. Performance enhancement beyond previous technologies will be needed regardless of the particular device architecture choice. Recent experiments and simulation have shown that as the transistor density increases it is even more challenging to achieve similar performance. Specifically, recent technologies have relied on local mechanical stress techniques to enhance channel mobility and thereby improve performance. As the transistor density increases, the size of features and the distance between features decreases. This situation limits the ability of stress enhancement techniques to have impact on channel mobility. Thus, new performance elements are also needed for future technology nodes. This presentation highlights the opportunities and challenges for 32nm Node CMOS and beyond.