Paper MN-TuP1
Effects of Gate Fabrication Processes on Electrical Characteristics in Suspended Gate FET

Tuesday, October 21, 2008, 6:30 pm, Room Hall D

Suspended gate FET`s (SG-FET) are expected to have a number of applications such as switching devices and acceleration sensors. A key process in these devices is how to fabricate the suspended gate. We have studied influence of the gate materials, the gate structure and sacrifice layer etching on the electrical characteristics of the SG-FET. The SG-FET we have developed has a conventional planar type MOS FET except for the gate placed apart from the silicon oxide gate insulator; the gate has a bridge structure with supports put outside the gate insulator. The gap between the gate and the gate insulator was designed to be 0.5 - 1.0μm. In these devices, the stress of the gate materials deforms the gate and changes the gap from the designed value; it affects the electrical characteristics of the SG-FET. Thus we have studied the gate materials and the gate structure to reduce deformation of the gate. Another important key in the SG-FET is the fabrication process of the suspended gate. To make its bridge structure, we deposit a sacrifice layer on the gate insulator first, and then deposit the gate material on it. After patterning it to form the gate, we remove the sacrifice layer by etching. This etching process affects the electrical characteristics of the SG-FET because of contamination and damage of the surface of the gate insulator. We applied polyimide to the sacrifice layer, and studied the influence of the etching method and the etching condition on the characteristics. In this presentation, we will discuss the relationship between the fabrication process and the materials of the suspended gate and the electrical characteristics in detail.