AVS 55th International Symposium & Exhibition
    MEMS and NEMS Monday Sessions
       Session MN+NC-MoA

Paper MN+NC-MoA3
Large-scale Fabrication of Silicon Nanowire NEMS Devices Using a Top-down Approach

Monday, October 20, 2008, 2:40 pm, Room 206

Session: Fabrication at the Micro- and Nano- Scales for MEMS/NEMS
Presenter: C.S. Roper, University of California, Berkeley
Authors: C.S. Roper, University of California, Berkeley
R.T. Howe, Stanford University
R. Maboudian, University of California, Berkeley
Correspondent: Click to Email

While bottom-up nanofabrication techniques, including vapor-liquid-solid (VLS) growth, can create single crystalline nanostructures,1 the integration of a single nanowire into a functioning, addressable device is an extremely difficult task, and problematic on a large scale, owing to the stochastic nature of the growth process. The primary barriers to bottom-up integration are manifold. First, nanowire placement and alignment are difficult to control. VLS nanowire growth is catalyzed by molten eutectic alloy nanoclusters that wander erratically on the substrate upon heating, and often coalesce with one another, rendering even size control unacceptably loose. Furthermore, transmission of signals to and from a nanostructure is problematic due to difficulty forming either directly contacted or capacitively coupled electrodes. Electron-beam lithography can be used to pattern electrodes on a bottom-up grown nanostructure to create a device,2 but its high cost and serial nature make it ineffectual for the realization of large arrays of interconnected devices. Unlike bottom-up techniques, top-down microfabrication techniques, including projection lithography, oxidation of silicon, chemical vapor deposition (CVD) of thin films, and plasma etching, readily lend themselves to precise placement, alignment, and ultra large scale integration. However, the minimum feature size and alignment error limitations of optical lithography preclude the direct patterning of nanoscale devices. We present a manufacturable fabrication process to realize large arrays of individually addressable silicon nanowire resonators using an entirely top-down approach that relies on optical projection lithography and multiple steps of controlled oxidation. Our fabrication process uses novel and elegant mask and process design to overcome the limitations of traditional top-down processes, yielding arrays of precisely positioned, vertically aligned, and electrically connected silicon nanowires with diameters as small as 30 nm. With the aim of creating ultra-sensitive mass sensors, devices with a single vertically aligned silicon nanowire as the resonant mass and multiple electrodes spaced hundreds of nanometers from the nanowire are also fabricated with the top-down process.

1J. Westwater et al., J. Vac. Sci. Technol. B., 15 (3) 554-557, 1997.
2 H. T. Soh, et al. Appl. Phys. Lett. 75, 627−629, 1999.