| AVS 55th International Symposium & Exhibition | |
| Electronic Materials and Processing | Thursday Sessions |
| Session EM-ThP |
| Session: | Electronic Materials and Processing Poster Session |
| Presenter: | S.M. Lee, Sungkyunkwan University, Korea |
| Authors: | S.M. Lee, Sungkyunkwan University, Korea B.I. Son, Sungkyunkwan University, Korea K.H. Eum, Sungkyunkwan University, Korea I.S. Chung, Sungkyunkwan University, Korea |
| Correspondent: | Click to Email |
We attempted to evaluate n+Si/SiO2/p-Si devices as a function of the thickness of SiO2. The thickness of SiO2 were varied from 2 nm to 5 nm. The breakdown of SiO2 layer in n+Si/SiO2/p-Si structure cause the device appears as pn+ junction diode. The simulated results using Silvaco TCAD also indicate that the currents of n+Si/SiO2/p-Si structures increase exponentially with respect to the applied voltage in the forward bias region. In addition, as the SiO2 breakdown is getting serious, the current-voltage curve moves toward the that obtained from ideal pn+ junction diode. The ratio in the current at 1.5 V between the breakdown device and the non-breakdown device reveals higher than 10000. The off state current in n+Si/SiO2/p-Si structure was simulated based on the direct tunneling model. The fabricated devices reveals similar characteristics. However, as the thickness of SiO2 layer decreases, the breakdown distribution and reliability tends to show worse results.