| AVS 55th International Symposium & Exhibition | |
| Applied Surface Science | Monday Sessions |
| Session AS-MoA |
| Session: | Electron Spectroscopies |
| Presenter: | W. Liu, Freescale Semiconductor Inc. |
| Authors: | W. Liu, Freescale Semiconductor Inc. S. Schauer, Freescale Semiconductor Inc. D. Theodore, Freescale Semiconductor Inc. H. Ramirez, Freescale Semiconductor Inc. |
| Correspondent: | Click to Email |
Auger depth profile analysis can be impeded by the roughening during ion sputtering. This is especially noticeable when analyzing semiconductor devices, because of the variety of materials that are susceptible to roughening, and the importance of very thin interfaces. A novel technique is presented in this paper, which combines scanning Auger analysis with FIB thinning, for analysis of single via interfacial structures in failure analysis of ICs devices. After a failing structure was identified by electrical fault isolation techniques, FIB sample preparation removes all the materials from top of the device including polyimide, passivation, metal layers, dielectric layers (ILD) until reaching about 200 Angstroms above the via interface in tungsten plug. Then a PHI SMART 200 scanning Auger instrument with a Physical Electronics model 06-350 ion gun was used for Auger depth profiling of this single via. A thin oxidized interface was observed between TiN glue layer and TiN ARC (anti-reflection coating) which resulted in the via failure. This layer would have been impossible to detect using conventional sputter depth profiling techniques. It was concluded from the following investigation and experiments that this interfacial material was caused by the “backsputtering” of ARC TiN during via etch and RF sputtering before TiN glue deposition.