Paper NS-FrM4
Shadow Edge Lithography for Wafer-Scale Nanomanufacturing

Friday, October 19, 2007, 9:00 am, Room 616

Many upcoming applications, such as nanoelectronic circuitry, single-molecule based chips, nanofluidics, chemical sensors, and fuel cells, require large arrays of nanochannels and nanowires. The commercialization of these state-of-the-art nanostructure-based devices, which are far superior to the microdevices, is challenged by the patterning consistence, throughput, and cost. For the purpose, we propose the shadow edge lithography (SEL) as a silicon (Si) wafer-scale nanomanufacturing method. The shadow effect of "line-of-sight" in high-vacuum evaporation is theoretically analyzed to predict the geometric distributions of the nanoscale patterns. Nanoscale patterns are created by the shadow of aluminum (Al) edges that are prepatterned using a conventional microfabrication method. Feasibility of the method is demonstrated by the fabrication of nanoscale gaps, which are further used to fabricate either arrays of nanochannels or nanowires on 4-inch Si wafers. The fabricated nanogaps have widths ranging from 15 nm to 100 nm on the 4-inch Si wafers using an e-beam evaporator (NRC 3117, Varian Inc., Palo Alto, CA). Considering the virtual source during the e-beam evaporation, the experimental results agree well with the theoretical prediction. Furthermore, by using the height differences in the pre-patterned Al edges to compensate the geometric distributions of the shadow effect, it is found that the uniformity tolerance in nanogap width can be 2 nm or 5% across the entire 4-inch Si wafers at a resolution down to 20 nm. Upon the nanogap fabrication, arrays of nanochannels are fabricated by reactive ion etching (RIE) using the e-beam evaporated Al layers as the etching mask; or arrays of chromium (Cr) nanowires are fabricated by depositing 15-nm Cr layer on the nanogap patterns followed by an Al lift-off. The fabricated Cr nanowires are further used as the RIE mask to produce arrays of Si nanowires on silicon-on-insulator (SOI) wafers. Our results show that that the evaporated Al layers can be used as the RIE or lift-off mask to transfer the nanoscale patterns with clear configuration and high yield. Thus, the proposed SEL provides a robust method for wafer-scale manufacturing for sub 50-nm structures, which may exceed the performance of the other nanopatterning methods. Because of the parallel processing nature of the SEL, it has a potential to become a key technology for massive nanomanufacturing with cost effectiveness.