Paper MN-TuM4
Fabrication of Reliable Through-Silicon via (TSV) Interconnects for 3D Stacking

Tuesday, October 16, 2007, 9:00 am, Room 615

The formation of through-silicon vias (TSVs) provides vertical interconnects that can be used in 3D stacking technology. A sloped via sidewall is essential for conformal coverage in subsequent deposition steps that provide insulation (SiO₂), barrier (TaN) and metal seed (Cu) layers. In this paper, varying via sidewall angles (82^o - 90^o) are investigated which allow variable degrees of conformal lining of the insulation, barrier and seed layers. The critical thickness of these lining layers that enable conformal coverage of the via sidewall is also investigated. Via insulation is deposited by plasma enhanced chemical vapor deposition (PECVD), while barrier and Cu metal seed layers are deposited by sputtering. A modified Bosch process using a deep reactive ion etch (DRIE) time multiplexing tool is used to create the different via profiles on 125 mm diameter silicon wafers. The cross-sectional view of via lining materials (SiO₂, TaN, and Cu) are examined with both an optical microscope and an environmental scanning electron microscope (ESEM). The via profile is examined using the ESEM. Furthermore, for a fixed via sidewall angle, variable aspect ratios are examined to determine the via profile that can be conformally lined and filled by Cu electroplating without any voids. The aspect ratios of the vias under study are 3, 4, 5, 6, and 8. Electrical performance and via integrity of the TSV process is also reported. Test structures are created during TSV processing that allow for a thorough study of interconnect reliability. This includes tests for via chain continuity, single via resistance, and via isolation.