Paper EM-ThP28
SEM Image Analysis and Resistance Measurements of Cu Via with Defects on a Test Wafer

Thursday, October 18, 2007, 5:30 pm, Room 4C

In LSI process, it is necessary for improvement of yield to inspect and analyze internal defects (e.g. void, etching-stop) of Cu interconnects after an electrical probing test. However, there are complicated and time-consuming procedures that consist of inspection of defects, samples making with focused ion beam (FIB) and cross section observation with scanning electron microscope (SEM). Therefore we have proposed more effective analysis system combined of SEM inspection and electrical probing equipment. This paper presents a relation between voltage contrast (VC) of SEM images and electrical resistance of via on a simple test wafer. The Via patterns of oxide (diameter of 160-300nm, depth of 500nm) were fabricated on double blanket layers which were made up of W layer (thickness of 200nm) to bring conductivity and SiO₂ layer to completely insulate from Si substrate. Next, TaN, Ta and Cu layer were buried in the via and planed with CMP at typical single damascene process. Two kinds of defects were in the via on the test wafer. With SEM inspection equipment and analyzing brightness of SEM images, these were classified into normal via and two kinds of defects via. Bright, gray and dark images of via correspond to normal, void and etch stop via respectively. Current-voltage (I-V) measurements of each via to calculate resistance were performed by electrical probing equipment with SEM, and one probe was contacted to W layer as ground line fabricated by FIB, another to Cu surface at the top of the via. First, I-V measurements were performed for normal via with a diameter of 160 - 300nm. The current, which was about 0.2mA at a voltage of 10mV, was continuous and ohmic, so it was sufficient to calculate a resistance. The resistance of several Ω was reasonable for a resistance generally performed in measurements of via chain. The resistance was in inverse proportion to the square of diameter, as expected, and its variation increased for small size via. Second, I-V measurements were performed for etch-stopped or void via with a diameter of 160nm. The resistance of void via was about 10 times of normal via and its variation was larger than variation of normal via. This suggests that variation of resistance dues to variation of void size in Cu. Furthermore, investigation of correlation between the resistance and brightness of SEM images presented numerically allows to know detailed information of defects. Finally, the combination of SEM inspection and electrical probing equipment can enable the estimate of resistance of via. In LSI process, it is possible to monitor defects directly and quantitatively by using SEM inspection equipment.