| AVS 54th International Symposium | |
| Electronic Materials and Processing | Thursday Sessions |
| Session EM-ThP |
| Session: | Electronic Materials and Processing Poster Session |
| Presenter: | P.-G. Jung, Chosun University, Korea |
| Authors: | P.-G. Jung, Chosun University, Korea Y.-K. Jun, Chosun University, Korea S.-H. Shin, Chosun University, Korea P.-J. Ko, Chosun University, Korea N.-H. Kim, Sungkyunkwan University, Republic of Korea W.-S. Lee, Chosun University, Korea |
| Correspondent: | Click to Email |
BLT thin films have many advantages such as highly fatigue resistance, low processing temperature, and large remanent polarization for high-density ferroelectric memories. However, the problems by plasma etching in patterning process of BLT thin films such as the angled sidewall preventing the densification of ferroelectric memory and being apt to receive the plasma damage were reported. Chemical mechanical polishing (CMP) process was proposed to fabricate the ferroelectric capacitor instead of plasma etching process for the vertical profile without plasma damage. CMP characteristics were presented in E-MRS 2006 spring meeting. CMP characteristics such as the removal rate and WIWNU% were improved by the increase of CMP pressure; however, the ferroelectric properties including polarization-electric field (P-E) characteristics of BLT capacitor fabricated by CMP process with the highest CMP pressure condition were disappeared. Bi content of BLT thin film was rapidly decreased as the increase of CMP pressure surface analysis. This means that Bi was easily removed in high CMP pressure. Therefore, the CMP pressure was controlled in CMP process for BLT thin film capacitor although the removal rate of BLT thin film became lower. Ferroelectric properties of BLT thin film capacitor were recovered with the vertical sidewall without the plasma damage. Acknowledgement: This work was supported by a Korea Research Foundation grant (KRF-2006-005-J00902).