Paper EM-ThP17
Pentacene TFTs with Ferroelectric Gate Insulators for Non-Volatile Memory Element

Thursday, October 18, 2007, 5:30 pm, Room 4C

Field effect transistors using ferroelectric materials as a gate insulator (FeFET) could be next generation-memory elements because of its attractive characteristics: non-volatile data retention, small size, non-destructive read-out, and fast programming speed. Recently, thin-film transistors (TFTs) with organic ferroelectric gate insulators have been studied since the fabrication of FeFET is possible at the low temperature compatible with glass substrates. While previous researches showed high performances in terms of good retentions and large hysteresis loop, they have some problems such as high programmable voltage (~100 V), a low mobility (~10^-3 cm²/V s). To overcome aforementioned drawbacks, we fabricated pentacene based FeFET with the gate insulator composed of stacking multi-layers. In this presentation, we report on the fabrication of pentacene thin-film transistor with a poly-4-vinylphenol (PVP)/ Poly(vinylidenefluoride/trifluoroethylene) (P(VDF/TrFE))/PVP triple-layer gate insulator. A triple-layer polymer gate insulator is deposited on an indium-tin oxide (ITO)/glass substrate by sequential spin-casting processes: 45 nm-thick PVP for a smoothing layer, 130 nm-thick P(VDF/TrFE) for a ferroelectric layer and 240 nm-thick PVP for a buffer layer. Each layer has own role for non-volatile memory thin file transistor. Our FeFET with the PVP/P(VDF/TrFE)/PVP triple layer exhibits a field effect mobility of 0.2 cm²/V s at each memory state and ~15V threshold voltage shift in the transfer characteristics which originates from the polarization of the ferroelectric layer by 50V writing voltage. The retention time was measured for 10⁴ second under constant read condition. More and advanced details will be discussed in coming presentation.