Paper MS-ThP5
Investigation of Multi-Level ReRAM in 65nm CMOS for Logic-in-Memory Applications

Thursday, October 24, 2019, 6:30 pm, Room Union Station B

Resistive Random Access Memory (ReRAM) has been extensively investigated as a non-volatile memory due to its low energy consumption and scalability. Bipolar ReRAM devices integrated in array architectures with selector devices is a prime candidate for high density memory arrays, novel logic-in-memory applications, and neuromorphic computation. Using a 65nm CMOS process technology, we have integrated 100 x 100 nm² HfO₂-based ReRAM devices at the metal 1 / via 1 (M1/V1) interface in a 1 transistor – 1 ReRAM (1T1R) configuration. Arrays of 1T1R cells were evaluated for binary switching between high resistance states (HRS) and low resistance states (LRS), exhibiting excellent yield and performance across a full 300mm wafer. Multi-level switching of 1T1R cells was then investigated by adjusting the gate voltage of the control transistor, which in turn, modulates the current compliance during programming (set operation) of the ReRAM device. Individual 1T1R cells within 8 x 8 arrays were programmed using increasing compliance current from 20 uA to 0.14 mA , which resulted in a 5-fold change in resistance level from 36 kOhm to 6.6 kOhm respectively. Multiple arrays from multiple 300 mm wafers have been evaluated to determine the variability within arrays, and the effects of changing processing conditions between wafers. Our results show that within a single wafer, 1T1R performance is consistent, but that variation in processing conditions for the HfO₂ switching layer can dramatically affect resistance levels and endurance of 1T1R. When comparing arrays on a single wafer, the standard deviation of the resistance state (for 100 switching cycles) decreased from 15 kOhm when programmed with current compliance of 20uA , to less than 500 Ohm at higher current compliance. Therefore, multiple distinguishable resistance states were achieved with higher current compliance. Using the two states (LRS and HRS), a 2 x 2 sub-array of 1T1R cells was then used to implement XOR logic functionality in a logic-in-memory configuration. Despite one of the cells having a low HRS not exceeding 20 kOhm, the output of the XOR logic was still unaffected. This demonstrates the robustness of logic-in-memory applications. The distinct binary state based logical computations, enabled by the appropriate selection of current compliance, also paves the way for ternary state logic and memory. Ongoing efforts are focused on higher precision control of the multi-level memory performance for 1T1R arrays up to 512 x 512 cells, and understanding the effects of wafer processing conditions on stochasticity of multi-level memory states, with the ultimate goal of full analog operation.