Invited Paper MS+EM+QS-ThM12
Neuromorphic Computing: From Emerging Devices to Neuromorphic System-on-a-Chip

Thursday, October 24, 2019, 11:40 am, Room A226

Several classes of emerging non-volatile memory (NVM) devices are currently being investigated for their application in analog implementation of artificial neural networks (ANN) hardware. The device can be two- or three-terminal and employ a wide range of material systems and associated physical mechanisms to achieve two or more non-volatile memory states. ANN hardware realizations include vector matrix multipliers (VMMs) and neural-inspired or Neuromorphic computing circuits. The NVM devices are employed in the form of crossbar or crosspoint arrays with or without selectors. In order to exploit the high-density and potential low-power operation of these devices, Analog circuit designers need to accommodate non-ideal behavior of these devices. This is particularly important for optimizing transistor-level circuit design for layout area, reliability, and static and dynamic power consumption. NVM nonidealities include device variability, low resistances offered by the two-terminal devices, finite resolution, relaxation of incremental states, limited dynamic range, and read/write endurance. This talk will provide an overview of Neuromorphic System-on-a-Chip (NeuSoC) that can be realized using emerging NVM arrays, expected device characteristics, associated circuit design challenges, and potential strategies for their mitigation. The talk will also include energy-efficiency estimation and benchmarking for NeuSoCs and provide pathways for future work in this area.