Paper EM+PS+TF-MoA1
Short-term Plasticity to Long-term Plasticity Transition Mimicked by High Mobility InP FETs with TiO₂ Trapping Layer

Monday, October 21, 2019, 1:40 pm, Room A214

Memory is widely believed to be encoded and stored in the central nervous system by altering the synapse strength via activity-dependent synaptic plasticity between millions of neurons in vertebrates. Consolidations from short-term plasticity (STP) to long-term plasticity (LTP) not only transform the important external stimuli to permanently stored information but release storage space for accepting new coming signals. Although memristor technology (e.g. RRAM) has been reported to mimic the STP and LTP characteristics and exhibited its merit in density comparing to traditional CMOS based SRAM technology, some conventional memristors suffer non-ideal operation speed, small dynamic range, and high resistance variation.

In our work, the single crystal Indium Phosphide (InP) based synaptic devices demonstrated its advantages not only in the emulation of the synaptic functions for both STP and LTP characteristics but also in the controllability of transition from STP to LTP. Since we interpret gate voltage pulses as the pre-synaptic action potentials, the source-drain current as post-synaptic current, and the channel conductance as synaptic weight, the consolidations from STP to LTP are elaborately demonstrated through mediating multiple action potential parameters like pulse numbers, pulse intervals (or rates), and pulse durations. The synaptic devices we demonstrated here are essentially single crystal channel InP Field Effect Transistors (FETs) fabricated on Si/SiO₂ substrates with the templated liquid-phase (TLP) method. In addition, TiO₂ trapping layer is inserted into the gate dielectric layer to provide extra deeper trap states. The ‘ratchet’ mechanism is utilized to have the charges ‘fall’ into the TiO₂ well and implement the transition from STP to LTP effectively.