Paper RM+EM+NS-TuA9
Indium Phosphide Synaptic Device on Silicon for Scalable Neuromorphic Computing

Tuesday, October 23, 2018, 5:00 pm, Room 203A

Inspired by the superior capability of the brain, neuronal spiking, and synaptic behavior have been mimicked by the CMOS-based neuronal cell in hardware, which contains 6-12 transistors depending on specific functionality and the robustness of the design. However, the higher energy consumption and physical area have led researchers to look for architectures based on single device and novel materials.

In our work, utilizing thin-film vapor-liquid-solid growth method, we fabricated scalable Indium phosphide (InP) channel transistors directly on Si/SiO₂ wafer, which can emulate significant synaptic characteristics such as elasticity, short- and long-term plasticity, metaplasticity, spike number dependent plasticity and spike timing dependent plasticity, by modeling gate electrode as the pre-synaptic axon terminal, the drain electrode as the post-synaptic dendrite, and the gate oxide-semiconductor channel as the synapse junction, in which we also interpreted the FET channel conductance as the synaptic weight.

We also demonstrated that by controlling the charging and discharging of interfacial traps at the gate oxide-semiconductor stack, we can essentially engineer hysteresis of the synaptic device to customize the synapse behavior and modify the synapse weight non-linearly. It underpins optimal selectivity of signal transduction and satisfies the key neuromorphic architecture characteristic—training and learn. Tuning hysteresis in a family of transfer characteristics in spike timing dependent plasticity (STDP) emulation, we attain maximum potentiation (depression) for the minimum positive (negative) interval time, which gradually decays down to elasticity, as we expected, indicating the scalable InP channel transistors on silicon as promising devices and platform for neuromorphic computation.