Invited Paper MS+MI+RM-TuM3
Memristive Synapses – Tuning Memristors for Performance and CMOS Integration

Tuesday, October 23, 2018, 8:40 am, Room 202B

Neuromorphic computing systems can achieve learning and adaptation in both software and hardware. The human brain achieves these functions via modulation of synaptic connections between neurons. Memristors, which can be implemented as Resistive Random Access Memory (ReRAM), are a novel form of non-volatile memory expected to replace a variety of current memory technologies and enable the design of new circuit architectures. Memristors are a prime candidate for so-called “synaptic devices” to be used in neuromorphic hardware implementations. A variety of challenges persist, however, for integrating memristors with CMOS, as well as for tuning device electrical performance. My research group has developed a fully CMOS-compatible integration strategy for ReRAM-based memristors on a 300 mm wafer platform, which can be implemented in both front-end-of-line (FEOL) and back-end-of-line (BEOL) configurations. With regard to memristor performance, we are focusing on strategies to reduce stochastic behavior during both binary and analog device switching. This is a key metric for neuromorphic applications, as variability in device conductance state directly influences the ultimate number of levels (weights) that can be implemented per synapse. Using a two pronged approach, we have developed device operational parameters to maximize analog performance, while also tuning the ReRAM materials stack and processing conditions to reduce stochasticity and optimize switching parameters (forming, set, and reset).