| AVS 65th International Symposium & Exhibition | |
| Electronic Materials and Photonics Division | Thursday Sessions |
| Session EM-ThP |
| Session: | Electronic Materials and Photonics Division Poster Session |
| Presenter: | Lucas Stucchi-Zucchi, University of Campinas, Brazil |
| Authors: | L. Stucchi-Zucchi, University of Campinas, Brazil A.R. Silva, University of Campinas, Brazil J.A. Diniz, University of Campinas, Brazil |
| Correspondent: | Click to Email |
Junctionless-FET (JL-FET) devices were fabricated on SOI substrate using NH4OH solution silicon etching as means to thin the channel substrate. The devices gate dielectric was silicon oxynitride grown using O2/N2 ECR (Electron-Cyclotron-Resonance) plasma, and its gate metal was TiN defined through lift-off and deposited using reactive sputtering. The electric contacts were fabricated with sputtered aluminum defined through lift-off and annealed on a conventional oven. Samples were characterized during the fabrication processes using optical microscopy and scanning electron microscopy (SEM). The device electrical performance was measured using a probestation and then cross-section SEM images were extracted using Ga+ Focused Ion Beam milling.
The final channel thickness was 65nm measured in the cross-section images, which also showed the angled sidewalls characteristic of the NH4OH solution wet etching. The channel dopant concentration was estimated at approximately 1017 atoms/cm3 through Pseudo-MOS electrical measurements, this was the doping concentration that was planned according to the simulation steps to ensure transistor behavior by sacrificing electrical contact quality. Electrical measurements showed transistor behavior and low leakage currents, despite the negative threshold voltage and poor electrical contacts, which distorted the I-V measurements due to their Schottky-like behavior. These results are as expected due to the measured channel thickness and the estimated channel dopant concentration and point favorably towards the silicon etching in NH4OH solution being a viable technique to fabricate JL-FET devices.
In the future, Atomic Force Microscopy (AFM) measurements will be used to measure the surface roughness after the silicon wet etching in NH4OH solution. With a more accurate etching rate, new samples will be fabricated with thinner channel thicknesses and higher dopant concentration. The enhanced fabrication process is expected to result in JL-FET devices that rival the performance of state-of-the-art MOSFET devices.
References
[1] J.P. Colinge et al., “Nanowire transistors without junctions”, Nature Nanotechnol. 5, p. 225-229 (2010).
[2] S. Migita, Y. Morita, T. Matsukawa, M. Masahara, and H. Ota, “Experimental Demonstration of Ultrashort-Channel (3 nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI”, IEEE Trans. on Nanotechnol., vol. 13, no. 2, p. 208-215 (2014).
[2] A. R. Silva, J. Miyoshi, J. A. Diniz, I. Doi and J. Godoy, “The Surface Texturing of Monocrystalline Silicon with NH4OH and Ion Implantation for Applications in Solar Cells Compatible with CMOS Technology.”, Energy Procedia, v. 44, p. 132-137 (2014).