| AVS 64th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Wednesday Sessions |
| Session PS-WeM |
| Session: | Advanced BEOL/Interconnect Etching |
| Presenter: | Xinghua Sun, TEL Technology Center, America, LLC |
| Authors: | X. Sun, TEL Technology Center, America, LLC T. Yamamura, TEL Technology Center, America, LLC A. Metz, TEL Technology Center, America, LLC P. Biolsi, TEL Technology Center, America, LLC H. Nagai, Tokyo Electron Limited PCDC, Japan R. Asako, Tokyo Electron Limited PCDC, Japan |
| Correspondent: | Click to Email |
In the traditional back end of line (BEOL) Dual Damascene structure integration, all-in-one-etch flow has been widely applied for successful interlayer metal connection. As technical node is being scaled down to 10/7nm, ever 5nm with lower K value (2.5), via chain chamfer profiles become more and more important to chip yield. However, once via mask organic is stripped off during all-in-one etch, chamfer corner extensively exposes to trench etching plasma damage resulted from radical or ion bombardment. Therefore, chamfer corner can be etched much faster than trench, resulting in seriously rounded and chopped chamfer corner. In addition, ultra low K material can be damaged by some plasma like organic strip plasma. After the trench etch/wet clean and metallization, the rounded and chopped chamfer corner can cause electrical short, remarkably lowering yield and reliability. Regarding this point, it is a very critical goal to minimize such rounding/damage of chamfer as much as possible.
We here present an atomic layer deposition (ALD)-SiO2 chamfer-less Dual Damascene flow. In this flow, a few nanometer ALD-SiO2 film is deposited around via after via opening. The SiO2 pillar left on via sidewall plays the role to protect the chamfer corner from seriously chopping and damage while the following etching. According to different applications, this SiO2 pillar height is controllable and completely etched off while trench process. This can significantly improve the chamfer angle/profile. The ALD-SiO2 chamfer-less-flow has a few advantages. First, ALD oxide material can be uniformly deposited on via sidewall and easily etched off with trench process. Second, trench is not affected since the ALD-SiO2 is deposited before organic layer stripping. Third, it is a simple integration flow as only one extra SiO2 deposition step is added. The last one is to prevent electrical short between via chain and underneath metal, which improves the chip yield/reliability.